AT89C51 电气专业外文翻译

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1、The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and

2、pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective s

3、olution to many embedded control applications. Function characteristic The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and

4、 clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Pow

5、er-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC：Supply voltage. GND：Ground. Port 0： Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When

6、1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash program

7、ming,and outputs the code bytes during programverification. External pullups are required during programverification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled h

8、igh by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directi

9、onal I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the inte

10、rnal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addres

11、ses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source fo

12、ur TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT8

13、9C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address du

14、ring accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur

15、ing each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller

16、is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

17、 EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for intern

18、al program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplif

19、ier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source,

20、 XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specificat

21、ions must be observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regi

22、sters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the int

23、ernal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle s

24、hould not be one that writes to a port pin or to external memory.Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mo

25、de is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabili

26、ze. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow

27、ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly 该AT89C51是一个低功耗，高性能CMOS 8位4K的闪存和可擦除可编程只读存

28、储器。该设备是采用Atmel的高密度非易失性存储器技术，并与兼容行业标准的MCS - 51指令集和引脚。片上闪存程序存储器可重新编程的系统或由传统的非易失性存储器编程。通过将通用的8位CPU与Flash在单片芯片，爱特梅尔AT89C51的是一个强大的微型计算机提供了一个高度灵活的和成本有效的解决方案许多嵌入式控制应用。 功能特点 该AT89C51提供以下标准特性：4K字节的闪存，128 MB内存，32余个字节/ O线，两个16位定时器/计数器，1个向量两级中断结构，全双工串行端口，片内振荡器和时钟电路。此外，AT89C51目的是为降低到零频率静态逻辑，支持两种软件可选省电模式。空闲模式停止的C

29、PU，同时允许的RAM，定时器/计数器，串行端口和中断系统继续运作。掉电模式保存RAM的内容，但冻结振荡器禁用直到下一次硬件复位所有其他片上功能。 引脚说明 虚拟通道连接：电源电压。 接地：接地。 端口0： 端口0是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可以吸收8 TTL输入。当1秒被写入端口0引脚，该引脚可作为高电平输入端。引脚 0也可以配置为低电平地址/在外部程序和数据存储器访问数据总线。在这种模式下P0有内部上拉电阻。引脚 0还收到了Flash编程的代码字节，在programverification和产出的代码字节。需要外部上拉过程中programverifica

30、tion。 端口1 端口1是一个8位双向I / O口与内部pullups.The端口1输出缓冲器可汇/源4 1秒的TTL inputs.When写入端口1它们拉高，由内部上拉电阻，可以引脚作为投入。作为输入，端口1引脚被外部退出是因为内部pullups.Port一低的电源电流（IIL的）也获得了闪存编程和核查的低位地址字节。 端口2 端口2是一个8位双向I / O口与内部pullups.The端口2输出缓冲器可汇/源4 1秒的TTL inputs.When写入端口2它们拉高，由内部上拉电阻，可以引脚作为投入。为输入，端口2个引脚被外部拉低的来源目前由于内部pullups.Port，2发出的高位

31、地址字节中提取从外部程序存储器以及在外部数据存储器访问，使用16位地址。在此应用程序，它使用的内部pullupswhen发射1秒。在访问外部数据存储器，使用8位地址，端口2排放的P2的特殊功能Register.Port 2的内容访问也收到了高地址位并在闪存编程和验证了一些控制信号。 端口3 端口3是一个8位双向I / O的内部pullups.The端口3输出缓冲器可吸收/源端口4 1秒的TTL inputs.When写入端口3它们拉高，由内部上拉电阻，可以引脚作为投入。作为投入，港3个管脚被外部拉因为pullups.Port三低的电源电流（IIL的），还担任了下面列出AT89C51的各种特殊功

32、能的功能： 端口3还收到闪存编程和验证了一些控制信号。 RST 复位输入。关于这两个机器周期针高，而振荡器运行重置设备。 啤酒/ PROG 联系地址锁存期间的外部存储器访问的地址低字节锁存使能输出脉冲。该引脚也脉冲输入的程序在正常运行闪存programming.In啤酒（PROG）被发射在恒定速率的1 / 6振荡器的频率，并且可以是外部定时或时钟的用途。但是，请注意，一个ALE脉冲被跳过每次到外部数据存储器访问。 如果需要，啤酒操作可以通过设置位SFR的位置8EH 0。随着位设置，ALE为活跃只在一执行MOVX或MOVC指令。否则，脚弱拉高。设置啤酒，禁用位没有任何效果，如果在外部微控制器执行

33、的模式。 的PSEN 程序存储使是读选通到memory.When的AT89C51的外部程序执行外部程序存储器的代码，被激活的PSEN每个机器周期的两倍，除了两个是激活的PSEN在每个外部数据存储器访问跳过。 行政助理/在线交流 外部访问启用。鄂必须捆绑至GND，以使该设备获取外部程序存储器的0000H到FFFFH起始位置的代码。但是请注意，如果锁定位1编程，艺电公司将在内部锁定在reset.EA应该绑内部程序executions.This到VCC引脚还收到12伏电压编程使（在线交流）在Flash编程，为部件require12伏在线交流。 XTAL1 输入到反相放大器和振荡器输入到内部时钟工作电

34、路。 XTAL2引脚 输出振荡器反相放大器。 振荡器特性 XTAL1和XTAL2是输入和输出，分别为一反相放大器可以配置为使用片上振荡器，如图1.Either石英晶体或陶瓷谐振器可以使用。为了推动从外部时钟源的设备，XTAL2引脚应该悬空而XTAL1驱动，如图所示顶置对外部时钟信号的占空比，因为内部时钟电路的输入通过一个没有要求分频2触发器，但最低和最高电压高，低时间规范必须遵守。空闲模式 在空闲模式下，提出自己的CPU睡觉而所有片上外设仍然很活跃。该模式是通过软件调用。内容上的片内RAM和所有特殊功能寄存器留在这个模式不变。在空闲模式可以被任何允许的中断或硬件reset.It应当指出，空闲时

35、是由硬制品复位终止终止的，设备恢复正常程序执行，从那里离开过，最多两个机器周期前内部复位控制算法的需要。在芯片硬件抑制访问这个事件的内部RAM，但访问端口引脚不是抑制。为了消除意外写入一个端口引脚时，空闲的可能性被重置终止，下列指令调用的那个空闲，不应该再写入到一个端口引脚或外部存储器。 掉电模式 在关断模式下，振荡器停止，并提示调用断电是最后一个指令执行。片上RAM和特殊功能寄存器保持到他们的价值观的权力模式下被终止。从权力的唯一出口，下一个硬件复位。重置重新定义了SFR，但不改变片内RAM。复位不应该被激活之前，VCC是恢复到正常操作水平，必须进行积极的长，足以使振荡器重新启动并稳定下来。 程序存储器锁定位 芯片上的三个锁，可留未编程（U）或可以通过编程（P）来获取下表中所列的其他功能位。 当锁定位1编程，在EA引脚的逻辑电平采样，并且在复位锁存。如果该设备是采用了无复位，锁存器初始化一个随机值，并认为被激活，直到重置价值。这是必要的EA的锁存值与目前在该引脚的逻辑，以便在设备水平协议是正常