基于单片机的档案库房温湿度监控系统设计
基于单片机的档案库房温湿度监控系统设计,基于,单片机,档案,库房,温湿度,监控,系统,设计
毕 业 设 计(论 文)任 务 书 设计(论文)题目:基于单片机的档案库房温湿度监控系统 学生姓名:发任务书日期:年月日 任务书填写要求1毕业设计(论文)任务书由指导教师根据各课题的具体情况填写,经学生所在专业的负责人审查、系(院)领导签字后生效。此任务书应在毕业设计(论文)开始前一周内填好并发给学生。2任务书内容必须用黑墨水笔工整书写,不得涂改或潦草书写;或者按教务处统一设计的电子文档标准格式(可从教务处网页上下载)打印,要求正文小4号 体,1.5 , 打印在 上 。3任务书内填写的内容,必须 学生毕业设计(论文) 的情况 一 , ,应 经 所在专业 系(院) 领导审 后 可 填写。4任务书内 学院 、 专业 名的填写,应写文,不写字。学生的 学号 要写号,不currency1写后2“或1“字。 5任务书内 要文 的填写,应按fifl 学院毕业设计(论文) 写的要求书写。 6 年月日 日期的填写,应 按fi标GB/T 740894fl据” 格式、 、日期 的要求,一用字书写。 2002年4月2日 或 2002-04-02”。毕 业 设 计(论 文)任 务 书1毕业设计(论文)课题应的目的: 的发人 生 生 所 的 要求 , 的库 , 、 库日 工 的 要内容, 库 的 要指标。 的用 工 可。 日 工 的 , 要 题 强库内温度与湿度的监测工 。但传统的 用与湿度、毛发湿度、双 属式测 计 湿度试 测试器材,通 人工 检测, 不符合温度 湿度要求的库房 通风、去湿 降温 工 。这种人工测试 费费力、效率低,且测试的温度 湿度误差大, 机大。此我 要一种造价低廉、用 便且测 准确的温湿度测 仪。由此 的基于单片机的温湿度测 仪开始出现在了人 的生 生 , 不断的发 将被大部分人所 受。课题设计一个温湿度监测系统,用于档案库房的温湿度监测,提醒库 员通风或除湿,温湿度传感器采用DTH11型传感器, 一种温湿度一体的字单总线传感器, 测 精度 且 较低,适合普通档案库房用,显器采用12864液晶显器。以单片机控制核心,外 硬件电路,将温湿度显 字控制集 于一体。实现 (减)温、 (除)湿的智控制。 2毕业设计(论文)课题任务的内容 要求(包括原始据、术要求、工 要求 ): 1. 用图书馆的书籍 网络 源查阅 单片机监控温湿度 内容的书籍 论文,依据要求 温湿度采集模块的设计;温湿度显模块的设计。 2. 设计要求设计 要包括硬件电路的设计 系统软件的设计。 硬件电路 要包括单片机、温湿度传感器、显模块、报警器以 控制设 5部分。 由DHT11温湿度传感器 12864液晶显器模块构 系统显模块;测温湿度控制电路由温湿度传感器 预设温度值比较报警电路组 ;用户根据 要预先输入预设值, 实际测 的温湿度不符合预设的温湿度标准,发出报警号(蜂鸣器蜂鸣),启动 应控制。 软件部分包括了 程序、显子程序、测温湿度子程序。 3.基功 检测温度、湿度 显温度、湿度 控制温度、湿度 毕 业 设 计(论 文)任 务 书3 毕业设计(论文)课题 果的要求包括图、实 硬件要求:学查找 应的 料,通 论 计算,得出优的设计 案。 1、详细 整的毕业设计说明书一份;2万字以上,且要符合要求; 2、 图 一套;设计图样部用AutoCAD绘制。 3、外文 料 译文一套。 4 要文: 1胡仁喜.Pro/ENGINEER Wildfire.化学工业出 .2010年4月( 一 ). 2 , .机器人术应用. 出 .2012年1月( ). 3 , , . 动检测与 术.机 工业出 .2002年1月( ). 4 .机电一体化术. 工业大学出 .2009年12月( 一 ). 5 , .液 传动与动术. 大学出 .2006年1月( 一 ). 6 、AutoCAD机 绘图基currency1教程与实. 大学出 .2007年8月( 一 ). 7“,fi.可fl程控制器. 大学出 .2010年3月( 一 ). 8 .电机与电控制.机 工业出 .2011年1月( 一 ). 9PLC应用术/ fl .- :人 电出 ,2010.10 10可fl程控制器应用术( ) fl: 13PLC电控制与组设计.”fl .- :学出 ,2003 4现电控制 PLC应用术. : 大学出 ,2000 14 生 fl. 电控制与可fl程控制器术. :化学工业出 .2004 2 15 .现电 可fl程控制术. : 大学出 .2002 毕 业 设 计(论 文)任 务 书5毕业设计(论文)课题工 度计 :2015.12.16-2016.1.10 发任务书、开题, 毕业实 2016.2.25-2.16.3.9 开题报、文译、论文大 2016.3.19-2016.4.25 提论文草 ,4月期检查 2016.4.26-2016.5.6 提论文 2016.5.6-2016.5.13 准 2016.5.13-2016.5.26 , ,改 所在专业审查 : 负责人: 2016 年 1 月 8 日毕 业 设 计(论 文)开 题 报 告 设计(论文)题目:基于单片机的档案库房温湿度监控系统 学生姓名: 年 月 日 开题报告填写要求 1开题报告(含“文献综述”)作为毕业设计(论文)答辩委员会对学生答辩资格审查的依据材料之一。此报告应在指导教师指导下,由学生在毕业设计(论文)工作前期内完成,经指导教师签署意见及所在专业审查后生效;2开题报告内容必须用黑墨水笔工整书写或按教务处统一设计的电子文档标准格式打印,禁止打印在其它纸上后剪贴,完成后应及时交 指导教师签署意见;3“文献综述”应按论文的 成文, 书写(或打印)在 开题报告 一 目内,学生写文献综述的 文献应 于15 ( );4 年月日 日期的填写,应 按 标GB/T 740894 据 交 格式 交 日期 时currency1的要求,一用“ 书写。fi“2004年4月26日”或“2004-04-26”。5 开题报告(文献综述)fl 按fl 书写, 1.5。 毕 业 设 计(论文) 开 题 报 告 1毕业设计(论文)”题,据所查 的文献资料, 写 于1000的文献综述: 1.目 意 档案 的 , 于 生资 。档案库房 的温度 湿度 对档案材料 的 度 要的 。对档案库房 的 的温度 湿度 及时的监控,档案 的 要 之一。控 档案库房温湿度的 , , 风 降湿相的办,控 库房温湿度的好办,传统的温湿度测量 过 工 检测,对 符温度 湿度要求的库房 风 去湿 降温 工作。费时 费力 效率低,且测试的温度及湿度误差大,随机性大。因此我们需要一种造价低廉 使用 便且测量准确的温湿度测量仪。目前在在档案房控技术上,主要 向 机界面的 性 设计 网络 控技术 面,集中在更 便的操作, 种 选控 式上, 用 机界面来使操作更容易。所 由单片机为核心的档案房温湿度控系统开始更好地为大家服务。2. 内外现状目前, 内大中型库房在仓 管 中由于技术 资金上的原因, 仅限于只对温度 监测, 温度超标时 强 风 翻仓,即使fi此,处 及时或因设备 力条件 限仍会造成大量损失。 现库房 藏物的升温主要由于湿度引起的,库房 藏物 身的水分过高或连续的高湿天气将导致 藏物新陈代谢加快而放出热量,放热引起的升温又使代谢 一步加剧 致发生霉 。这种恶性循 一旦形成难 效的控。因此,库房在 温度监测的同时,必须 视空气湿度的检测, 利于提前 效 施控库房 藏物升温而霉 。 文设计温湿度控系统由单片机为控核心,传感器 讯 电子技术, 现了温湿度的 效监测,降低经济损失 劳动强度。据档案房 藏物的需要,部分甚完 的 ,使 为 造 的 的 动控技术 成为主 。此时的 内 完整的控系统, 种传感器集温 据,监控系统 时监测 及控 机 的动作, 好的 机界面使管 的操作过 形 而且 便。这种控系统需要管 档案 所要求 的目标 ,计 机据传感器的 测量 设currency1的目标 , currency1温 因子的控过 ,控相应机 降温 风 动作。计 机 动控的温 控技术 现了监管 动 ,劳动生 率 提高。 过 档案 设currency1目标 , 动地 内 气 。我 大部分 主开发的大型现代 温湿度监管系统引 的, 外设备 于这种控 式。 3. 文献 1.单片机原 及应用M, currency1天currency1空大学出“.2007.2 2传感器原 fi设计 应用M,: fl 技大学出“,2005:205-207 3成,新, . 传感器 动检测技术M .:高 教出“,2006 4新型单片机AT89C2051及其应用 J 1996年 04期 5金. DS18B20 现高”度温度测量J. 电子报, 2005, (2005-02-27) 6 , .传感器 处 M.:电子工业出“,1998 7家, . 单片机 及应用技术M .:高 教出“,2006 8 单片机原 及 技术M,:大学出“,1996.7 9 . 动控原 及其应用M,:高 教出“,2004 10 . 动检测技术M,:机 工业出“,2000 11 单片机的C 应用 设计M,:currency1空currency1天大学出“,2003.11 12 .单片机原 及应用J,:高 教出“.2004 13 .电动机的单片机控.currency1空currency1天大学出“.2004 14 .集成传感器应用.中 电力出“.2005.10 15 .单片机应用 分 M,:currency1空currency1天大学出“.2003 毕 业 设 计(论文) 开 题 报 告 2 ”题要或 的 题 用的 (): 1.工作务分 件电 主要由单片机 DHT11温湿度传感器 12864 器 报器及控设备 5部分 成。测温湿度控电 由温湿度传感器 设温度 报电 成;用 需 设 , 测量的温湿度 符 设的温湿度标准时,由 器发出报 , 动相应控。 系统将档案库房的温湿度 据集 发 处 器 分 处 , 超出 设 后,控系统发出使报系统 动,提 外界 工 。 主要 成 温湿度集部分,单片机控部分 及报系统。 2.毕业设计目 施及 度 1-2 : 相 文献资料及写毕业设计开题报告。 3-4 :优 集电 设计 5-6 :文献 设计 报及控电 7-8 : 一步 文献,系统软件的设计, 主 模块 温湿度集模块 据转 处 模块 报控子 模块 模块及主 处 9-12 :仿真分 新的电 , 提 出 的模型 工艺 。 13-14 :写毕业设计报告,准备毕业答辩。 15 :毕业答辩。 毕 业 设 计(论文) 开 题 报 告 指导教师意见:1对“文献综述”的评 :文献综述符毕业设计要求,对 ”题的 内外发展叙述 为详细。 2对 ”题的深度 广度及工作量的意见 对设计(论文)果的 测: ”题的深度 广度及工作量符毕业设计要求。相 过该生努力顺利完成设计。 3.否同意开题: 同意 同意 指导教师: 2016 年 03 月 08 日所在专业审查意见:同意 负责 : 2016 年 04 月 05 日毕 业 设 计(论 文)外 文 参 考 资 料 及 译 文 译文题目:The General Situation of AT89C51 AT89C51应用学生姓名: 专 业: 所在学院: 指导教师: 职 称: AT89C51的概况The General Situation of AT89C51Chapter 1 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil lator disabling all other chip functions until the next hardware reset.Figure 1-2-1Block Diagram1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0:Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification.Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outputbuffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG:Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN:Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPP:External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit. XTAL2 :Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. 2.1Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPUs window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.翻译AT89C51的概况1 AT89C51应用单片机广泛应用于商业:诸如调制解调器,电动机控制系统,空调控制系统,汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而,这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51 汽车单片机多线性测试环境。这种环境的目标不仅是为AT89C51 汽车单片机提供一种健壮测试环境,而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。开发的这种环境连接了AT89C51。本文讨论了这种测试环境的设计和原理,它的和各种硬件、软件环境部件的交互性,以及如何使用AT89C51。1.1 介绍8 位AT89C51 CHMOS 工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51 单片机典型的应用是高速事件控制系统。商业应用包括调制解调器,电动机控制系统,打印机,影印机,空调控制系统,磁盘驱动器和医疗设备。汽车工业把MCS51 单片机用于发动机控制系统,悬挂系统和反锁制动系统。AT89C51 尤其很好适用于得益于它的处理速度和增强型片上外围功能集,诸如:汽车动力控制,车辆动态悬挂,反锁制动和稳定性控制应用。由于这些决定性应用,市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器,服务大量时间和事件驱动的在实时应用需要的集成外围的能力,具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场,尤其任务决定性应用诸如自动驾驶仪或反锁制动系统,错误将是财力上所禁止的。重新设计的费用可以高达500K 美元,如果产品族享有同样内核或外围设计缺陷的话,费用会更高。另外,部件的替代品领域是极其昂贵的,因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题,在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。Intel Chandler 平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行的测试类型。1.2 AT89C51提供以下标准功能:4k 字节FLASH 闪速存储器,128 字节内部RAM,32 个I/O 口线,2 个16 位定时/计数器,一个5 向量两级中断结构,一个全双工串行通信口,片内振荡器及时钟电路。同时,AT89C51 降至0Hz 的静态逻辑操作,并支持两种可选的节电工作模式。空闲方式体制CPU 的工作,但允许RAM,定时/计数器,串行通信口及中断系统继续工作。掉电方式保存RAM 中的内容,但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。 图1-2-1 AT89C51 方框图1.3引脚功能说明Vcc:电源电压GND:地P0 口:P0 口是一组8 位漏极开路型双向I/O 口,也即地址/数据总线复用。作为输出口用时,每位能吸收电流的方式驱动8 个TTL 逻辑门电路,对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时,这组口线分时转换地址(低8 位)和数据总线复用,在访问期间激活内部上拉电阻。在Flash 编程时,P0 口接受指令字节,而在程序校验时,输出指令字节,校验时,要求外接上拉电阻。P1 口:P1 是一个带内部上拉电阻的8 位双向I/O 口,P1 的输出缓冲级可驱动(吸收或输出电流)4 个TTL 逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。Flash 编程和程序校验期间,P1 接受低8 位地址。P2 口:P2 是一个带有内部上拉电阻的8 位双向I/O 口,P2 的输出缓冲级可驱动(吸收或输出电流)4 个TTL 逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。在访问外部程序存储器或16 位四肢的外部数据存储器(例如执行MOVX DPTR指令)时,P2 口送出高8 位地址数据,在访问8 位地址的外部数据存储器(例如执行MOVX RI 指令)时,P2 口线上的内容(也即特殊功能寄存器(SFR)区中R2 寄存器的内容),在整个访问期间不改变。Flash 编程和程序校验时,P2 也接收高位地址和其他控制信号。P3 口:P3 是一个带有内部上拉电阻的8 位双向I/O 口,P3 的输出缓冲级可驱动(吸收或输出电流)4 个TTL 逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作为输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)。P3 口还接收一些用于Flash 闪速存储器编程和程序校验的控制信号。RST:复位输入。当振荡器工作时,RST 引脚出现两个机器周期以上高电平将使单片机复位。ALE/PROG:当访问外部程序存储器或数据存储器时,ALE(地址锁存允许)输出脉冲用于锁存地址的低8 位字节。即使不访问外部存储器,ALE 仍以时钟振荡频率的1/6 输出固定的正脉冲信号,因此它可对外输出时钟或用于定时目的。要注意的是,每当访问外部数据存储器时将跳过一个ALE 脉冲。对Flash 存储器编程期间,该引脚还用于输入编程脉冲(PROG)。如有必要,可通过对特殊功能寄存器(SFR)区中的8EH 单元D0 位置位,可禁止ALE 操作。该位置位后,只有一条MOVX 和MOVC 指令ALE 才会被激活。此外,该引脚会被微弱拉高,单片机执行外部程序时,应设置ALE 无效。PSEN:程序存储允许输出是外部程序存储器的读选通型号,当89C51 由外部存储器取指令(或数据)时,每个机器周期两次PSEN 有效,即输出两个脉冲。在此期间,当访问外部数据存储器,这两次有效的PSEN 信号不出现。EA/VPP
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