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1、-hdb3_coder.vhd,实现HDB3编码器功能library ieee;use ieee.std_logic_1164.all;entity hdb3_coder isport(codein:in std_logic; clk:in std_logic; clr:in std_logic; codeout:out std_logic_vector(1 downto 0);end hdb3_coder;architecture rtl of hdb3_coder issignal codeoutv:std_logic_vector(1 downto 0);signal count0:in
2、teger:=0;signal s0:std_logic_vector(4 downto 0):=00000;signal count1:integer range 1 downto 0;signal codeoutb:std_logic_vector(1 downto 0);signal s1:std_logic_vector(4 downto 0):=00000;signal clkb:std_logic;signal s3:std_logic_vector(1 downto 0);signal flag1b:integer range 1 downto 0;signal flagv:in
3、teger range 1 downto 0;signal firstv:integer range 0 to 1;component dff-调元件dff port(d:in std_logic; clk:in std_logic; q :out std_logic);end component;begin add_v:process(clk,clr) -插V begin if(rising_edge(clk)then if(clr=1)then codeoutv=00; count0codeoutv=01; -01代表1 count0 if(count0=3)then -四连0插v cod
4、eoutv=11; count0=0; else count0=count0+1; codeoutv codeoutv=00; count0=count0; end case; end if; end if;end process add_v;s0(0)=codeoutv(0);s1(0)=codeoutv(1);dsll:dff port map(s1(0),clk,s1(1);ds01:dff port map(s0(0),clk,s0(1);dsl2:dff port map(s1(1),clk,s1(2);ds02:dff port map(s0(1),clk,s0(2);dsl3:d
5、ff port map(s1(2),clk,s1(3);ds03:dff port map(s0(2),clk,s0(3);-dsl4:dff port map(s1(3),clk,s1(4);-ds04:dff port map(s0(3),clk,s0(4);-dsl5:dff port map(s1(4),clk,s1(5);-ds05:dff port map(s0(4),clk,s0(5);bclk:clkb=not clk;add_b:process(clkb) -插B begin if(rising_edge(clkb)then if(codeoutv=11)then if(fi
6、rstv=0)then count1=0; firstv=1; s1(4)=s1(3); s0(4)=s0(3); else if(count1=0)then s1(4)=1; s0(4)=0; count1=0; else s1(4)=s1(3); s0(4)=s0(3); count1=0; end if; end if; elsif(codeoutv=01)then count1=count1+1; s1(4)=s1(3); s0(4)=s0(3); else s1(4)=s1(3); s0(4)=s0(3); count1=count1; end if; end if; end pro
7、cess add_b;codeoutb=s1(4)&s0(4);output:process(clkb) -输出 begin if(rising_edge(clkb)then if(codeoutb=01)or(codeoutb=10)then -1或B if(flag1b=1)then codeout=01; flag1b=0; else codeout=11; flag1b=1; end if; elsif(codeoutb=11)then -V if(flag1b=1)then codeout=11; else codeout=01; end if; else codeout=00; flag1b=flag1b; end if; end if; end process output;end rtl;
数字基带信号HDB3码的编码器设计与建模
