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1、基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK ; Jian程序library IEEE;use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating - any Xilinx primitives in this code. -library UNISIM;-use UNISIM.VComponents.all; entity lcd is
2、 port(clk, reset : in bit;SF_D : out bit_vector(3 downto 0);LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit; LED : out bit_vector(7 downto 0) ); end lcd;architecture behavior of lcd istype tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done); signal tx_state : tx_sequence := don
3、e; signal tx_byte : bit_vector(7 downto 0); signal tx_init : bit := 0;type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done); signal init_state : init_sequence := idle; signal init_init, init_done : bit := 0; signal i : integer range 0 to 750000 := 0; signal i2
4、 : integer range 0 to 2000 := 0; signal i3 : integer range 0 to 82000 := 0;signal SF_D0, SF_D1 : bit_vector(3 downto 0); signal LCD_E0, LCD_E1 : bit; signal mux : bit;type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g,char_a, done)
5、;signal cur_state : display_state := init; beginLED -The following -when to transmit a command/data and when not to with cur_state selecttx_init -control the bus with cur_state select mux -control the initialization sequence with cur_state select init_init 0 when others;-register select with cur_sta
6、te selectLCD_RS -what byte to transmit to lcd-refer to datasheet for an explanation of these values with cur_state selecttx_byte display: process(clk, reset) beginif(reset=1) thencur_state elsif(clk=1 and clkevent) then case cur_state is-refer to intialize state machine below when init =if(init_done
7、 = 1) then cur_state cur_state -every other state but pause uses the transmit state machine when function_set = if(i2 = 2000) thencur_state cur_state end if;when entry_set = if(i2 = 2000) thencur_state cur_state when set_display = if(i2 = 2000) thencur_state cur_state when clr_display = i3 if(i2 = 2
8、000) then cur_state cur_state when pause = if(i3 = 82000) then cur_state cur_state when set_addr = if(i2 = 2000) then cur_state cur_state when char_J = if(i2 = 2000) then cur_state cur_state when char_I = if(i2 = 2000) then cur_state cur_state end if;when char_A= if(i2 = 2000) then cur_state cur_sta
9、te when char_N = if(i2 = 2000) then cur_state cur_state when done = cur_state end process display; with mux selectSF_D LCD_E transmit : process(clk, reset, tx_init) beginif(reset=1) then tx_state elsif(clk=1 and clkevent) then case tx_state iswhen high_setup = -40ns LCD_E0 SF_D0 tx_state tx_state when high_hold = -230ns LCD_E0 SF_D0 tx_state tx_state when oneus = LCD_E0 tx_state tx_state when low_setup = LCD_E0 SF_D0 tx_state tx_state when low_hold = LCD_E0 SF_D0 tx_state when fortyus = LCD_E0 tx_state
基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK
