南京理工大学EDA设计2

EDA设计II 史耀亮 电子工程与光电技术学院 0810210232EDA设计实验报告基于QuartusII的多功能数字钟设计 院系：电子工程与光电技术学院专业：电子信息工程学号：0810210232姓名：史耀亮指导老师：蒋立平时间：2011年4月25日4月28日多功能数字钟摘要：利用QuartusII软件采用模块化设计方法、自顶向下设计理念，设计一个具有24小时计时功能的电子钟。实验全部用VHDL语言编写。软件仿真调试成功后编译下载至可编程实验系统SmartSOPC中进行硬件测试。实现并充分领略硬件设计软件化的精髓。关键词：数字钟 模块化 硬件 Abstract：Using the QuartusII software to design a digital-bell that has timing function for 24 hours with modular design method and top-down concept. The whole experiment is written in VHDL. After emulating and debugging successfully, translate and edit the code. Then, download the result to the programmable SmartSOPC system and test in hardware. Realizing the soul of designing hardware by software.Key word: digital-bell modular hardware目录一、 设计内容简介-3二、 设计要求-3三、 方案论证（整体电路设计原理）-3四、 子模块设计原理-41、 脉冲产生电路-42、 计时电路-53、 显示电路-104、 清零电路-145、 校时校分电路-146、 整点报时电路-157、 闹钟设定电路-168、 音乐闹钟电路-179、 电路模块总图-21五、 实验中遇到的问题及解决方法-28六、 结论-29七、 实验心得-29八、 参考文献-29一、 设计内容简介设计一个数字钟，可以完成24小时的计时功能，并在控制电路的作用下具有清零、快速校分、快速校时、整点报时、音乐闹钟等功能。二、 设计要求1、 基本要求（1） 能进行正常的时分秒计时功能；（2） 分别由六个数码管显示时、分、秒的计时；（3） 可进行系统的清零操作；（4） 可进行系统的快速校分操作；（5） 可进行系统的快速校时操作；提高部分要求（1） 时钟具有整点报时功能（当时钟计时到5953时开始报时，在5953、5955、5957时报时频率为1KHZ，在5959时报时频率为3KHZ）；（2） 闹钟设定功能；（3） 音乐闹钟功能；三、 方案论证本实验在实现实验基本功能的基础上，加入了整点报时、音乐闹钟功能。下图为实验功能方框图：数字计时器基本功能是计时。整个数字计时器的计数部分共包括6位：时十位、进个位、分十位、分个位、秒十位和秒个位。首先需要获得具有精确振荡时间的脉冲振荡信号，以此作为计时电路的时序基础。本实验可以使用的振荡频率源为48MHZ，通过分频获得所需脉冲频率（1HZ，1KHZ，3KHZ）。其中1HZ用来作为时、分、秒的时钟端。设计一个模60模块，对1HZ脉冲进行秒计数，产生秒位；同时用秒位的进位信号作为分位即另一个模60模块的使能端；而分的进位信号则用来作为小时的使能端，小时是一个模24的模块。显示功能采用动态显示。通过一组控制信号与6个显示块相连。当前显示数码块用低电平选通后，即对该位进行译码并将译码结果送上数码管，从而显示数字。清零电路采用高电平工作、低电平清零模式。用一个变量控制计数模块内部的显示值。当清零端为高电平时，计数器内部的显示值正常跳变；当清零端为低电平时，即强制该值为0。从而实现了清零功能。校分校时电路采用信号通知机制。当校分键切换至0时，即通过两个变量分别通知秒位与时位停止计数，而分接收的进位信号则恒为1，每一秒跳变一次。直至校分键切换至0，恢复正常计数。校时键工作流程及原理与校分键同。整点报时功能可以通过组合逻辑电路实现，在VHDL中即用一个逻辑表达式对计数器中特定的时刻送出的高电平信号进行与、或、非的运算，从而产生一个选通信号，将指定的频率信号送入蜂鸣器中，实现在规定的时刻以特定频率发音报时，当时钟计时到5953时开始报时，在5953、5955、5957时报时频率为1KHZ，在5959时报时频率为3KHZ。闹钟设定功能。闹钟只设定时和分，基本模块与正常计时电路里的校时校分电路相同。设定一个闹钟使能键，按下该键后进入闹钟设定界面，此时校分校时开关用于调节闹钟时间，对正常计时没有影响，且此时七段数码管显示的是闹钟时间，恢复使能键后对设定的闹钟时间没有影响。闹钟设定了一个开关键，可以在闹钟响铃的一分钟其间将其关掉。音乐闹钟功能即闹钟的声音用音乐实现。用一个使能端与音乐模块相连，当闹钟时间与当前显示时间值相等时，使能端即置为高电平。音乐模块接收到该信号，就开始启动。输出信号与整点报时功能信号或之后接入蜂鸣器。音乐模块工作时产生一个4Hz的节拍信号。随后把七个音节对应的频率分别赋值给七个变量。根据网上下载的曲谱进行编码。从而完成整个音乐模块功能。四、 子模块设计原理1、 脉冲电路产生原理实验板上振荡源为48MHZ，为获得秒脉冲信号和报时电路中需要的音频，需要对该振荡进行分频处理。处理的过程示意如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Hz_1 ISPORT(CLK_IN:IN STD_LOGIC; CLK_OUT:OUT STD_LOGIC);END Hz_1;ARCHITECTURE FUN OF Hz_1 ISSIGNAL NUMBER:INTEGER RANGE 0 TO 24000000;SIGNAL CURRENT_CLK:STD_LOGIC;BEGINCLK_OUT<=CURRENT_CLK;PROCESS(CLK_IN)BEGINIF CLK_IN 'EVENT AND CLK_IN='1' THENIF NUMBER<24000000 THENNUMBER<=NUMBER+1;ELSENUMBER<=0;CURRENT_CLK<=NOT CURRENT_CLK;END IF;END IF;END PROCESS;END FUN;通过以上代码，即可将48MHz的信号分频成为一个1Hz的信号。分频成1KHz信号的代码与此类似，此处不再赘述。具体实现过程：对脉冲信号的上升沿进行计数，当上升沿来到，NUMBER值即加1，当达到所需值时，内部时钟翻转，同时将内部时钟信号对外输出。2、 计时电路时钟能够产生时间前进是对秒脉冲计数产生形成的，为了形成时分秒，需要对秒进位信号进行计数从而产生分，对分进位信号进行计数产生时信号。秒和分均为60进制，时为24进制，所以需要有模60和模24计数模块。模60计数秒模块代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Second_60 ISPORT(CLK_MAIN:IN STD_LOGIC;CLK_SPEED:IN STD_LOGIC:='1'CHECK_M_F:IN STD_LOGIC:='1'CHECK_H_F:IN STD_LOGIC:='1'KONGZHI:IN STD_LOGIC:='0'JINWEI:OUT STD_LOGIC:='0'ZB_53:OUT STD_LOGIC:='0'ZB_55:OUT STD_LOGIC:='0'ZB_57:OUT STD_LOGIC:='0'ZB_59:OUT STD_LOGIC:='0'SECOND_HIGH:OUT INTEGER RANGE 0 TO 5;SECOND_LOW:OUT INTEGER RANGE 0 TO 9);END Second_60;ARCHITECTURE FUN OF Second_60 ISSIGNAL CURRENT_VALUE:INTEGER RANGE 0 TO 59;CONSTANT LING:INTEGER:=0;BEGINPROCESS(CURRENT_VALUE)BEGINIF KONGZHI='0' THENIF CURRENT_VALUE<10 THENSECOND_HIGH<=0;SECOND_LOW<=CURRENT_VALUE;ELSIF CURRENT_VALUE<20 THENSECOND_HIGH<=1;SECOND_LOW<=CURRENT_VALUE-10;ELSIF CURRENT_VALUE<30 THENSECOND_HIGH<=2;SECOND_LOW<=CURRENT_VALUE-20;ELSIF CURRENT_VALUE<40 THENSECOND_HIGH<=3;SECOND_LOW<=CURRENT_VALUE-30;ELSIF CURRENT_VALUE<50 THENSECOND_HIGH<=4;SECOND_LOW<=CURRENT_VALUE-40;ELSESECOND_HIGH<=5;SECOND_LOW<=CURRENT_VALUE-50;END IF;ELSESECOND_HIGH<=LING;SECOND_LOW<=LING;END IF;END PROCESS;PROCESS(CLK_MAIN,CLK_SPEED,CHECK_M_F,CHECK_H_F)BEGINIF CLK_SPEED='1' AND CHECK_M_F='1' AND CHECK_H_F='1' THENIF CLK_MAIN 'EVENT AND CLK_MAIN='1' THENIF CURRENT_VALUE=52 THENZB_53<='1'ELSEZB_53<='0'END IF;IF CURRENT_VALUE=54 THENZB_55<='1'ELSEZB_55<='0'END IF;IF CURRENT_VALUE=56 THENZB_57<='1'ELSEZB_57<='0'END IF;IF CURRENT_VALUE=58 THENJINWEI<='1'ZB_59<='1'ELSE JINWEI<='0'ZB_59<='0'END IF;IF CURRENT_VALUE=59 THEN CURRENT_VALUE<=0;ELSE CURRENT_VALUE<=CURRENT_VALUE+1;END IF;END IF;ELSIF CLK_SPEED='0' THENCURRENT_VALUE<=0;ELSENULL;END IF;END PROCESS;END FUN;模60计数分模块与此类似，此处不再赘述。模24计数时模块代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Hour_24 ISPORT(CLK_MAIN:IN STD_LOGIC;CLK_SPEED:IN STD_LOGIC:='1'CHECK_IN:IN STD_LOGIC:='0'KONGZHI:IN STD_LOGIC:='0'NAOLING_H:OUT STD_LOGIC:='0'CHECK_S_T_H:OUT STD_LOGIC:='0'ENABLE1:IN STD_LOGIC:='0'ENABLE2:IN STD_LOGIC:='0'HOUR_HIGH:OUT INTEGER RANGE 0 TO 2;HOUR_LOW:OUT INTEGER RANGE 0 TO 9);END Hour_24;ARCHITECTURE FUN OF Hour_24 ISSIGNAL CURRENT_VALUE1:INTEGER RANGE 0 TO 23;SIGNAL CURRENT_VALUE2:INTEGER RANGE 0 TO 23:=23;BEGINPROCESS(CURRENT_VALUE1,CURRENT_VALUE2)BEGINIF KONGZHI='0' THENIF CURRENT_VALUE1<10 THENHOUR_HIGH<=0;HOUR_LOW<=CURRENT_VALUE1;ELSIF CURRENT_VALUE1<20 THENHOUR_HIGH<=1;HOUR_LOW<=CURRENT_VALUE1-10;ELSEHOUR_HIGH<=2;HOUR_LOW<=CURRENT_VALUE1-20;END IF;END IF;IF KONGZHI='1' THENIF CURRENT_VALUE2<10 THENHOUR_HIGH<=0;HOUR_LOW<=CURRENT_VALUE2;ELSIF CURRENT_VALUE2<20 THENHOUR_HIGH<=1;HOUR_LOW<=CURRENT_VALUE2-10;ELSEHOUR_HIGH<=2;HOUR_LOW<=CURRENT_VALUE2-20;END IF;END IF;IF CURRENT_VALUE1=CURRENT_VALUE2 THENNAOLING_H<='1'ELSENAOLING_H<='0'END IF;END PROCESS;PROCESS(CLK_MAIN,CLK_SPEED,ENABLE1,ENABLE2,KONGZHI)BEGINIF ENABLE1='1' AND ENABLE2='1' AND CLK_SPEED='1' THENIF CLK_MAIN 'EVENT AND CLK_MAIN='1' THENIF CURRENT_VALUE1=23 THEN CURRENT_VALUE1<=0;ELSE CURRENT_VALUE1<=CURRENT_VALUE1+1;END IF;IF KONGZHI='1' THENIF CURRENT_VALUE2=23 THEN CURRENT_VALUE2<=0;ELSE CURRENT_VALUE2<=CURRENT_VALUE2+1;END IF;END IF;END IF;ELSIF CLK_SPEED='0' THENCURRENT_VALUE1<=0;IF KONGZHI='1' THENCURRENT_VALUE2<=0;END IF;ELSENULL;END IF;END PROCESS;PROCESS(CHECK_IN)BEGIN IF CHECK_IN='1' THENCHECK_S_T_H<='0'ELSECHECK_S_T_H<='1'END IF;END PROCESS;END FUN;波形仿真图如下：3、 显示电路采取动态显示方式。由Cycle模块产生位选信号组，用低电平选通数码块，然后由Led_deng模块根据位选信号的不同，选择对时高位、时低位、分高位、分低位、秒高位、秒低位之一进行译码，然后将译码信号和位选信号送上数码管进行显示。显示电路之片选模块Cycle代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Cycle ISPORT(CLK:IN STD_LOGIC;CYCLE_ZHI:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END Cycle;ARCHITECTURE FUN OF Cycle ISSIGNAL TEMP:INTEGER RANGE 0 TO 5;BEGINPROCESS(CLK)BEGINIF CLK 'EVENT AND CLK='1' THENIFTEMP<5THENTEMP<=TEMP+1;ELSE TEMP<=0;END IF;END IF;END PROCESS;PROCESS(TEMP)BEGINCASE TEMP ISWHEN 0=>CYCLE_ZHI<="111110"WHEN 1=>CYCLE_ZHI<="111101"WHEN 2=>CYCLE_ZHI<="111011"WHEN 3=>CYCLE_ZHI<="110111"WHEN 4=>CYCLE_ZHI<="101111"WHEN 5=>CYCLE_ZHI<="011111"END CASE;END PROCESS;END FUN;显示电路之译码模块Led_deng代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Led_deng ISPORT(CHOOSE_BEGIN:IN STD_LOGIC_VECTOR(5 DOWNTO 0);DATA_IN1:IN INTEGER RANGE 0 TO 9;DATA_IN2:IN INTEGER RANGE 0 TO 9;DATA_IN3:IN INTEGER RANGE 0 TO 9;DATA_IN4:IN INTEGER RANGE 0 TO 9;DATA_IN5:IN INTEGER RANGE 0 TO 9;DATA_IN6:IN INTEGER RANGE 0 TO 9;CHOOSE_LAST:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);DATA_OUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END Led_deng;ARCHITECTURE FUN OF Led_deng ISCONSTANT SEG_SHOW_0:STD_LOGIC_VECTOR(6 DOWNTO 0):="1000000"CONSTANT SEG_SHOW_1:STD_LOGIC_VECTOR(6 DOWNTO 0):="1111001"CONSTANT SEG_SHOW_2:STD_LOGIC_VECTOR(6 DOWNTO 0):="0100100"CONSTANT SEG_SHOW_3:STD_LOGIC_VECTOR(6 DOWNTO 0):="0110000"CONSTANT SEG_SHOW_4:STD_LOGIC_VECTOR(6 DOWNTO 0):="0011001"CONSTANT SEG_SHOW_5:STD_LOGIC_VECTOR(6 DOWNTO 0):="0010010"CONSTANT SEG_SHOW_6:STD_LOGIC_VECTOR(6 DOWNTO 0):="0000010"CONSTANT SEG_SHOW_7:STD_LOGIC_VECTOR(6 DOWNTO 0):="1111000"CONSTANT SEG_SHOW_8:STD_LOGIC_VECTOR(6 DOWNTO 0):="0000000"CONSTANT SEG_SHOW_9:STD_LOGIC_VECTOR(6 DOWNTO 0):="0011000"BEGIN PROCESS(DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,CHOOSE_BEGIN)BEGINIF CHOOSE_BEGIN="111110" THENCASE DATA_IN1 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;IF CHOOSE_BEGIN="111101" THENCASE DATA_IN2 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;IF CHOOSE_BEGIN="111011" THENCASE DATA_IN3 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;IF CHOOSE_BEGIN="110111" THENCASE DATA_IN4 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;IF CHOOSE_BEGIN="101111" THENCASE DATA_IN5 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;IF CHOOSE_BEGIN="011111" THENCASE DATA_IN6 ISWHEN 0=>DATA_OUT<=SEG_SHOW_0;WHEN 1=>DATA_OUT<=SEG_SHOW_1;WHEN 2=>DATA_OUT<=SEG_SHOW_2;WHEN 3=>DATA_OUT<=SEG_SHOW_3;WHEN 4=>DATA_OUT<=SEG_SHOW_4;WHEN 5=>DATA_OUT<=SEG_SHOW_5;WHEN 6=>DATA_OUT<=SEG_SHOW_6;WHEN 7=>DATA_OUT<=SEG_SHOW_7;WHEN 8=>DATA_OUT<=SEG_SHOW_8;WHEN 9=>DATA_OUT<=SEG_SHOW_9;WHEN OTHERS=>DATA_OUT<="0111111"END CASE;END IF;CHOOSE_LAST<=CHOOSE_BEGIN;END PROCESS;END FUN;4、 清零电路清零电路即设置一个开关变量，当置为1时，电路正常计时；当置为0时，电路清零。具体代码已包含在计时电路中。5、 校分校时电路校分校时电路也是设置几个变量，当校时开关置为1时，即通知秒和分位停止计数。时的进位信号置为1。校分原理相同。其中计算进位信号的门电路真值表如下：AB C010000011011111011A：本位所得进位信号 B:非本位传给本位的校时或校分信号 C:本位的校时或校分信号进位信号计算模块Men代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Men IS PORT(T:IN STD_LOGIC;TT:IN STD_LOGIC;TTT:IN STD_LOGIC;TTTT:OUT STD_LOGIC);END Men;ARCHITECTURE FUN OF Men ISSIGNAL TEMP1: STD_LOGIC;SIGNAL TEMP2: STD_LOGIC;SIGNAL TEMP3: STD_LOGIC;BEGINPROCESS(T,TT,TTT)BEGINTEMP1<=NOT T;TEMP2<=TEMP1 OR TT;TEMP3<=NOT TEMP2;TTTT<=TTT OR TEMP3;END PROCESS;END FUN;6、 整点报时电路整点报时功能可以通过组合逻辑电路实现，在VHDL中即用一个逻辑表达式对计数器中特定的时刻送出的高电平信号进行与、或、非的运算，从而产生一个选通信号，将指定的频率信号送入蜂鸣器中，实现在规定的时刻以特定频率发音报时，当时钟计时到5953时开始报时，在5953、5955、5957时报时频率为1KHZ，在5959时报时频率为3KHZ。整点报时的逻辑表达式：整点报时模块逻辑函数模块函数代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Zyumen IS PORT(T1:IN STD_LOGIC;T2:IN STD_LOGIC;T3:IN STD_LOGIC;T4:IN STD_LOGIC;T5:IN STD_LOGIC;T6:IN STD_LOGIC;T7:IN STD_LOGIC;TT:OUT STD_LOGIC);END Zyumen;ARCHITECTURE FUN OF Zyumen ISSIGNAL TEMP1:STD_LOGIC;SIGNAL TEMP2:STD_LOGIC;SIGNAL TEMP3:STD_LOGIC;SIGNAL TEMP4:STD_LOGIC;SIGNAL TEMP5:STD_LOGIC;BEGINPROCESS(T1,T2,T3,T4,T5,T6,T7)BEGINTEMP1<=T2 OR T3;TEMP2<=TEMP1 OR T4;TEMP3<=TEMP2 AND T6;TEMP4<=T5 AND T7;TEMP5<=TEMP3 OR TEMP4;TT<=T1 AND TEMP5;END PROCESS;END FUN;7、 闹钟设定电路闹钟设定电路需在时分内部各自另设一个变量作为闹钟的计时变量，当闹钟计时变量与当前显示时间值时分位相等时，即启动闹钟。响铃时间为1分钟，中途可关掉闹钟。当切换至闹钟显示界面时，即将闹钟的计时变量译码后送入数码管。使用校时校分开关设定闹钟作用时间。闹钟设定功能模块代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Naoling ISPORT(GUAN_NAO:IN STD_LOGIC:='1'NAOLING_QIE:IN STD_LOGIC;NAOLING_M:IN STD_LOGIC;NAOLING_H:IN STD_LOGIC;KONGZHI:OUT STD_LOGIC;DATA_OUT0:OUT STD_LOGIC);END Naoling;ARCHITECTURE FUN OF Naoling ISBEGINPROCESS(NAOLING_QIE)BEGINIF NAOLING_QIE='1' THENKONGZHI<='1'ELSEKONGZHI<='0'END IF;END PROCESS;PROCESS(NAOLING_M,NAOLING_H,GUAN_NAO)BEGINIF NAOLING_M='1' AND NAOLING_H='1' AND GUAN_NAO='1' THENDATA_OUT0<='1'ELSE DATA_OUT0<='0'END IF;END PROCESS;END FUN;8、 音乐闹钟电路用一个使能端与音乐模块相连，当闹钟时间与当前显示时间值相等时，使能端即置为高电平。音乐模块接收到该信号，就开始启动。输出信号与整点报时功能信号或之后接入蜂鸣器。音乐模块工作时需产生一个4Hz的节拍信号。音乐模块代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY music ISPORT(M:IN STD_LOGIC;CLK1,CLK1L: IN STD_LOGIC;BEEP: OUT STD_LOGIC);END music;ARCHITECTURE BEH OF music ISTYPE STATE_TYPE IS (DO_M,RE_M,MI_M,FA_M,SOL_M,LA_M,SI_M,DO_H,RE_H,MI_H,FA_H,SOL_H,LA_H,SI_H,NONE);SIGNAL COUNTER : INTEGER RANGE 0 TO 100000 := 0; SIGNAL COUNT : INTEGER RANGE 0 TO 280 := 0; SIGNAL BEEP_REG: STD_LOGIC;SIGNAL CLK14HZ,MM: STD_LOGIC;SIGNAL NOTE : STATE_TYPE ; BEGINPROCESS(M)BEGINIF M='1' THENBEEP <= BEEP_REG ;ELSE BEEP<='0'END IF; END PROCESS; BEEP_PRO : PROCESS(CLK1) VARIABLE CNT : INTEGER RANGE 0 TO 100000 := 0; BEGIN IF (CLK1'EVENT AND CLK1='1') THEN IF CNT < COUNTER THEN CNT := CNT + 1 ; ELSE CNT := 0 ; BEEP_REG <= NOT BEEP_REG; END IF; END IF; END PROCESS BEEP_PRO; CLK14HZ_PRO :PROCESS(CLK1L) VARIABLE CNT : INTEGER RANGE 0 TO 124 := 0; BEGIN IF (CLK1L'EVENT AND CLK1L = '1') THEN IF CNT = 124 THEN CNT := 0 ; CLK14HZ <= NOT CLK14HZ; ELSE CNT := CNT + 1; END IF; END IF; END PROCESS CLK14HZ_PRO; COUNT_PRO : PROCESS(CLK14HZ) BEGIN IF (CLK14HZ'EVENT AND CLK14HZ ='1') THEN IF COUNT <= 127 THEN COUNT <= COUNT + 1; ELSE COUNT<=0; END IF; END IF; END PROCESS COUNT_PRO; NOTE_PRO : PROCESS(NOTE) BEGIN CASE NOTE IS WHEN DO_M => COUNTER <= 47774 ; WHEN RE_M => COUNTER <= 42568 ; WHEN MI_M => COUNTER <= 37919 ; WHEN FA_M => COUNTER <= 35791 ; WHEN SOL_M => COUNTER <=31888 ; WHEN LA_M => COUNTER <= 28409 ; WHEN SI_M => COUNTER <= 25309 ; WHEN DO_H => COUNTER <= 23912 ; WHEN RE_H => COUNTER <= 21282 ; WHEN MI_H => COUNTER <= 18961 ; WHEN FA_H => COUNTER <= 17897 ; WHEN SOL_H => COUNTER <=15944 ; WHEN LA_H => COUNTER <= 14205 ; WHEN SI_H => COUNTER <= 12605 ; WHEN OTHERS => COUNTER <= 0; END CASE; END PROCESS NOTE_PRO; MUSIC_PRO : PROCESS(COUNT) BEGIN CASE COUNT IS WHEN 0|1 => NOTE <= SOL_H; WHEN 2 => NOTE <= MI_H; WHEN 3 => NOTE <= FA_H; WHEN 4|5 => NOTE <= SOL_H; WHEN 6 => NOTE <= MI_H; WHEN 7 => NOTE <= FA_H; WHEN 8 => NOTE <= SOL_H; WHEN 9 => NOTE <= SOL_M; WHEN 10 => NOTE <= LA_M; WHEN 11 => NOTE <= SI_M; WHEN 12 => NOTE <= DO_H; WHEN 13 => NOTE <= RE_H; WHEN 14 => NOTE <= MI_H;WHEN 15 => NOTE <= FA_H;WHEN 16|17 => NOTE <= MI_H; WHEN 18 => NOTE <= DO_H;WHEN 19 => NOTE <= RE_H;WHEN 20|21 => NOTE <= MI_H;WHEN 22 => NOTE <= MI_M;WHEN 23 => NOTE <= FA_M;WHEN 24 => NOTE <= SOL_M;WHEN 25 => NOTE <= LA_M;WHEN 26 => NOTE <= SOL_M;WHEN 27 => NOTE <= FA_M;WHEN 28 => NOTE <= SOL_M;WHEN 29 => NOTE <= MI_M;WHEN 30 => NOTE <= FA_M;WHEN 31 => NOTE <= SOL_M;WHEN 32|33 => NOTE <= FA_M;WHEN 34 => NOTE <= LA_M;WHEN 35 => NOTE <= SOL_M;WHEN 36|37 => NOTE <= FA_M;WHEN 38 => NOTE <= MI_M;WHEN 39 => NOTE <= RE_M;WHEN 40 => NOTE <= MI_M;WHEN 41 => NOTE <= RE_M;WHEN 42 => NOTE <= DO_M;WHEN 43 => NOTE <= RE_M;WHEN 44 => NOTE <= MI_M;WHEN 45 => NOTE <= FA_M;WHEN 46 => NOTE <= SOL_M;WHEN 47 => NOTE <= LA_M;WHEN 48|49 => NOTE <= FA_M;WHEN 50 => NOTE <= LA_M;WHEN 51 => NOTE <= SOL_M;WHEN 52|53 => NOTE <= LA_M;WHEN 54 => NOTE <= SI_M;WHEN 55 => NOTE <= DO_H;WHEN 56 => NOTE <= SOL_M;WHEN 57 => NOTE <= LA_M;WHEN 58 => NOTE <= SI_M;WHEN 59 => NOTE <= DO_H;WHEN 60 => NOTE <= RE_H;WHEN 61 => NOTE <= MI_H;WHEN 62 => NOTE <= FA_H;WHEN 63 => NOTE <= SOL_H;WHEN 64|65=> NOTE <= MI_H;WHEN 66 => NOTE <= DO_H;WHEN 67 => NOTE <= RE_H;WHEN 68|69=> NOTE <= MI_H;WHEN 70 => NOTE <= RE_H;WHEN 71 => NOTE <= DO_H;WHEN 72 => NOTE <= RE_H;WHEN