基于某MIPS指令地单周期微控制器设计哈工大

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1、word课程设计说明书论文课程名称：数字集成系统课程设计 设计题目：基于MIPS指令的单周期微控制器设计院 系： 航天学院 微电子科学与技术系 班 级：设 计 者：学 号：指导教师：设计时间：2015年7月27日-2015年8月7日 姓 名： 院 系： 专 业： 班 号： 任务起至日期： 2015 年 7 月 27 日 至 2015 年 8 月 7 日课程设计题目：基于MIPS指令的单周期微控制器设计技术参数和设计要求：Load/store，算术逻辑运算和流程控制是RISC的主要组成局部，本设计以MIPS指令子集为例，研究RISC的根本原理与硬件建模。（1） load/store设计设计要求：

2、参考计算机组成与设计硬件/软件接口，进展模块划分和设计微控制器整体结构，设计支持load、store指令的数据通路，并比拟各种实现的效率、面积和速度。（2） 算术逻辑运算设计设计要求：设计支持add、sub、multi、or等指令的数据通路。（3） 流程控制设计设计要求：设计支持branch、jump等指令的数据通路。（4） 基于MIPS指令的单周期微控制器设计设计要求：同组同学共同完成具有10条左右指令的单周期微控制器设计。根本要求：1确定设计采用的结构2划分所确定的结构，画出模块图，确定模块间的连接关系，端口方向与宽度3确定设计的验证方案，验证点与验证向量4完成设计的RTL建模与测试平台建

3、模5完成设计的验证、逻辑综合，给出设计的评价面积、速度6完成设计报告工作量：本课程设计按照每4人一组分工协作完成。每位成员完成设计要求中的13任务之一，作为独立完成项，在完成个人项目根底上共同完成设计要求中的第4项。熟悉开发环境、学习EDA工具使用：10学时分析题目、确定设计方案：5学时设计、验证、综合以与结果分析、整理数据：25学时工作计划安排：2015.7.28 学习modelsim、Designpiler使用方法2015.7.30 分析设计题目，确定结构与模块划分2015.8.6 完成设计、验证、综合与性能分析 2015.8.7 提交课程设计报告 同组设计者与分工： 指导教师签字_ 年

4、月 日 教研室主任意见： 教研室主任签字_ 年 月 日*注：此任务书由课程设计指导教师填写。文档一、 功能描述基于MIPS指令的单周期微控制器设计：l_w和s_w指令的实现：控制器实现支持load word(lw)、store word(sw)指令的MIPS单周期数据通路： l_w：存放器rs中的数据和立即数imm相加，得到存储器地址，用这个地址访问存储器，把得到的存储器数据写入存放器rt中。把PC + 4写入PC。 s_w：存放器rs中的数据和立即数imm相加，得到存储器地址，把存放器rt中的数据写入这个地址的存储器中。把PC + 4写入PC。二、 设计方案：1. 整体框图：2. 模块划分：

5、如下图中，各个大模块中还包含：立即数符号位扩展，存放器堆，存储器，ALU，指令存放器，PC，控制部件3. 模块连接框图：4. 总体设计思想：我设计的局部主要包三四局部，分别为：指令存放器、存放器堆、和存储器，额外还有一个Alu，即加法器和一个pc，即程序计数器，是借助同组同学编译的程序。存取指令需要两个状态单元，计算下一个指令地址需要一个加法器，两个状态单元分别是指令存放器和程序存放器。指令存放器是制度的，任意时刻的输出都反映了输入的地址的内容，而不需要读控制信号。程序计数器是一个32位的存放器，让在每个时钟周期末都会被写入。加法器被设计为只进展加法运算的ALU，他将输入的俩个32位数相加将结

6、果输出。Mips指令执行时，首先需要的是指令存储器，用来存储指令，并根据所给地址提供指令，指令地址存放在pc中，pc的设计还需要一个加法器来指向下一个指令的地址。在执行R型指令时，读两个存放器，对他们中的内容进展Alu操作，再写出结果。处理器的32个存放器组成一个存放器堆的结构，即register。在读取指令的时候，一般形式为：op rs rt imm，此时需要将一个16位的立即数带符号扩大为32位，然后和rs地址内的内容通过Alu加法器相加，如果是读取指令即load word ,即得出的是存储器地址，将得出的存储器地址内的内容写入rt所指的存放器地址处，如果是存储指令即store word，

7、即得出的存储器地址用来写入rt地址内的所存内容。5. PC程序计数器：6. L_w电路图：7. L_w的设计思想： sw rt, imm(rs) ; memoryrs+(sign)imm read_file -format verilog /home/homeO5/user1/dbf4/alu.v /home/homeO5/user1/dbf4/control.v /home/homeO5/user1/dbf4/cpu_top.v /home/homeO5/user1/dbf4/l_s.v /home/homeO5/user1/dbf4/pc.v /home/homeO5/user1/dbf4

8、/regfile.vLoading verilog files: /home/homeO5/user1/dbf4/alu.v /home/homeO5/user1/dbf4/control.v /home/homeO5/user1/dbf4/cpu_top.v /home/homeO5/user1/dbf4/l_s.v /home/homeO5/user1/dbf4/pc.v /home/homeO5/user1/dbf4/regfile.v Detecting input file type automatically (-rtl or -netlist).Running DC verilo

9、g readerReading with Presto HDL piler (equivalent to -rtl option).Running PRESTO HDLCWarning: /home/homeO5/user1/dbf4/alu.v:13: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/control.v:7: Port aluc is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4

10、/control.v:8: Port pcsource is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/control.v:29: the undeclared symbol i_lw assumed to have the default net type, which is wire. (VER-936)Warning: /home/homeO5/user1/dbf4/control.v:30: the undeclared symbol i_sw assumed to have the default net t

11、ype, which is wire. (VER-936)Warning: /home/homeO5/user1/dbf4/cpu_top.v:16: the undeclared symbol wmem assumed to have the default net type, which is wire. (VER-936)Warning: /home/homeO5/user1/dbf4/cpu_top.v:23: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/

12、cpu_top.v:61: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/l_s.v:11: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/pc.v:4: Port pcin is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:5: Port pc4 is

13、implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:8: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/pc.v:17: Port pc_in is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:17: Port qa is implicitly typed (VER-987)Warning: /home/ho

14、meO5/user1/dbf4/pc.v:18: Port imm1 is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:19: Port imm2 is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:21: Port pc_out is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:22: Port select is implicitly type

15、d (VER-987)Warning: /home/homeO5/user1/dbf4/regfile.v:13: The statements in initial blocks are ignored. (VER-281)Statistics for case statements in always block at line 13 in file /home/homeO5/user1/dbf4/alu.v=| Line | full/ parallel |=| 23 | auto/auto |=Warning: /home/homeO5/user1/dbf4/l_s.v:11: Pot

16、ential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:14: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Inferred memory devices in process in routine DataMem line 12 in file /home/ho

17、meO5/user1/dbf4/l_s.v.=| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| register_reg | Latch | 32 | Y | N | N | N | - | - | - | register_reg | Latch | 32 | Y | N | N | N | - | - | - |=Statistics for MUX_OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| DataMem/11

18、 | 256 | 32 | 8 | N |=Warning: /home/homeO5/user1/dbf4/l_s.v:158: do20:16 is being read, but does not appear in the sensitivity list of the block. (ELAB-292)Warning: /home/homeO5/user1/dbf4/l_s.v:159: do15:11 is being read, but does not appear in the sensitivity list of the block. (ELAB-292)Statisti

19、cs for case statements in always block at line 154 in file /home/homeO5/user1/dbf4/l_s.v=| Line | full/ parallel |=| 157 | auto/auto |=Warning: /home/homeO5/user1/dbf4/l_s.v:144: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/db

20、f4/l_s.v:145: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:146: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:147: Potential simula

21、tion-synthesis mismatch if index exceeds size of array register. (ELAB-349)Statistics for MUX_OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| InstMem/144 | 128 | 1 | 7 | N |=Inferred memory devices in process in routine pc line 8 in file /home/homeO5/user1/dbf4/pc.v.=| Register Name

22、 | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| pc4_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |=Warning: /home/homeO5/user1/dbf4/pc.v:34: qa is being read, but does not appear in the sensitivity list of the block. (ELAB-292)Statistics for case statements in always block at line 30 in

23、file /home/homeO5/user1/dbf4/pc.v=| Line | full/ parallel |=| 31 | auto/auto |=Warning: /home/homeO5/user1/dbf4/regfile.v:13: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/regfile.v:14: Potential simulation-synthesis misma

24、tch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/regfile.v:19: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Inferred memory devices in process in routine regfile line 16 in file /home/homeO5/user1/dbf4/regfile.v.=|

25、Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

26、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

27、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

28、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

29、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

30、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N |

31、 N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |=Statistics for MUX_OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| regfile/13 | 32 | 32 | 5 | N | regfile/14 | 32 | 32 | 5 | N |=Presto pilation pleted su

32、ccessfully.Current design is now /home/homeO5/user1/dbf4/alu.db:aluWarning: Overwriting design file /home/homeO5/user1/dbf4/DataMem.db. (DDB-24)Warning: Overwriting design file /home/homeO5/user1/dbf4/InstMem.db. (DDB-24)Loaded 11 designs.Current design is alu.design_vision Current design is alu.10.

33、功能综合：Report : areaDesign : cpu_topDate : Fri Aug 7 08:43:23 2015*Library(s) Used: typical (File: /export/homeO5/libs/smic18/std_cell/2005q4v1/aci/sc-x/synopsys/typical.db)Number of ports: 1Number of nets: 368Number of cells: 10Number of references: 10Net Interconnect area: undefined (No wire load sp

34、ecified)Total area: undefinedReport : timing -path full -delay max -max_paths 1Design : cpu_topDate : Fri Aug 7 08:42:50 2015* # A fanout number of 1000 was used for high fanout net putations.Operating Conditions: typical Library: typicalWire Load Model Mode: top Startpoint: r1/register_reg132 (risi

35、ng edge-triggered flip-flop clocked by clk) Endpoint: r1/register_reg19 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Point Incr Path - r1/register_reg132/CK (EDFFX1) 0.00 # 0.00 r r1/register_reg132/QN (EDFFX1) 0.31 0.31 f r1/U84/Y (OAI222XL) 0.21 0.52 r r1/U210/Y

36、(NOR3X1) 0.08 0.60 f r1/U208/Y (OAI21XL) 0.72 1.31 r r1/qb2 (regfile) 0.00 1.31 r s1/a2 (Select_0) 0.00 1.31 r s1/U18/Y (AOI22X1) 0.04 1.36 f s1/U17/Y (INVX1) 0.16 1.52 r s1/outp2 (Select_0) 0.00 1.52 r a1/i12 (alu) 0.00 1.52 r a1/r65/B2 (alu_DW01_addsub_0) 0.00 1.52 r a1/r65/U4/Y (XOR2X1) 0.15 1.67

37、 f a1/r65/U1_2/CO (ADDFX2) 0.30 1.98 f a1/r65/U1_3/CO (ADDFX2) 0.20 2.18 f a1/r65/U1_4/CO (ADDFX2) 0.20 2.38 f a1/r65/U1_5/CO (ADDFX2) 0.20 2.58 f a1/r65/U1_6/CO (ADDFX2) 0.20 2.78 f a1/r65/U1_7/CO (ADDFX2) 0.20 2.97 f a1/r65/U1_8/CO (ADDFX2) 0.20 3.17 f a1/r65/U1_9/CO (ADDFX2) 0.20 3.37 f a1/r65/U1

38、_10/CO (ADDFX2) 0.20 3.57 f a1/r65/U1_11/CO (ADDFX2) 0.20 3.77 f a1/r65/U1_12/CO (ADDFX2) 0.20 3.97 f a1/r65/U1_13/CO (ADDFX2) 0.20 4.17 f a1/r65/U1_14/CO (ADDFX2) 0.20 4.37 f a1/r65/U1_15/CO (ADDFX2) 0.20 4.57 f a1/r65/U1_16/CO (ADDFX2) 0.20 4.77 f a1/r65/U1_17/CO (ADDFX2) 0.20 4.97 f a1/r65/U1_18/CO (ADDFX2) 0.20 5.17 f a1/r65/U1_19/CO (ADDFX2) 0.20 5.37 f a1/r65/U1_20/CO (ADDFX2) 0.20 5.57 f a1/r65/U1_21/CO (ADDFX2) 0.20 5.76 f a1/r65/U1_22/CO (ADDFX2) 0.20 5.96 f a1/r65/U1_23/CO (ADDFX2) 0.20 6.16 f a1/r65/U1_24/CO (ADD