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1、毕业设计/论文外 文 文 献 翻 译 基于FPGA的数字信号发生器的设计 在现代电子测量技术的研究及应用领域中，常常需要高精度且参数可调的信号源。数字信号发生器已成为现代测量领域应用最为广泛的通用仪器之一，代表了信号源的发展方向。而随着大规模可编程逻辑器件FPGA的发展以及可编程片上系统（SOPC）设计技术的日渐成熟，为这类信号发生器的设计与实现提供了理论依据与技术支持。本文设计的数字信号发生器以直接数字频率合成（DDS）技术为核心，用现场可编程门阵列（FPGA）来实现频率和相位的预置和改变，并完成信号的频率和相位差显示。设计中采用的是直接数字频率合成（DDS）技术，该技术是一项关键的数字技术

2、，能很好的实现信号在幅度，频率以及相位等方面的移动。系统以EDA软件为工具，采用VHDL语言，满足了对数字信号控制的更高要求。结果表明，采用EDA技术设计的数字信号发生器使得数控系统与其他的电路实现的数字信号发生器相比具有更高的可靠性、实时性、运算速度高以及集成度高等特点。该数字信号发生器的设计可像软件一样随时更改，这就为系统维护带来了方便，同时结合FPGA有效地扩展输出波形的频率范围，实现了输出两路高精度相位差的正弦信号，使系统性能稳定可靠。 关键词：信号发生器；DDS；片上可编程系统；FPGA；1 导言FPGA本质上是一种数字设备。然而，随着FPGA的资源合理使用，使用FPGA进行数字化多

3、通道模拟波形成为了一种可能。数字化的波形可直接在FPGA内部处理。目前有几种模拟信号数字化的可能的方案。我们计划在FPGA 模数转换器的研究中使用一种基于在图1所示的斜坡比较的方法。图1 基于FPGA的模数转换器模拟输入均直接连接到FPGA的输入引脚。一个无源RC网络连接到FPGA的输出引脚，以便生成定期参考电压斜坡。当参考电压斜坡到达输入电压等级时，差分输入缓冲器被用作比较器来产生FPGA内部逻辑转换。转换时间是通过TDC块在FPGA中实现被数字化的。从这段时间以后，RC网络参数和坡道起动时间可以从已知的输入电压大小而得到。如今，FPGA器件被设计成与各种差分信号标准兼容以后，差分输入缓冲器

4、由于其有效的大的输入电压范围成为了很好的比较器。许多基于比较器的ADC方案可以用FPGA来实现。例如，通过计划，在较大的FPGA资源使用下（通常是每通道4个I / O引脚），信号可以被迅速地跟踪，并且只产生很小的数字化误差。随着威尔金森破败的计划，负责窄脉冲一体化可以用数字化来结合，尽管越来越多的外部模拟电路是必要的。我们在此研究的斜坡比较方案（或者在分类借鉴基础上的单斜坡ADC，尽管这两个坡道的斜坡可以被利用）是对于相对缓慢的信号大通道数的应用的一种合适的选择。 （在一些参考资料里，单斜坡计划被误认为是参照基于双斜坡原则的威尔金森ADC。）一个关键的功能块，时间数字转换器（TDC）在FPGA

5、是需要的。有两种TDC方案可以在FPGA中实现：延迟链方案和多采样方案。我们在这项工作中使用的TDC是涉及四时钟的多采样方案。在参考文献7中提到，四个抽样，边缘检测，脉冲滤波器和计数锁存器是由四个90度相分离时钟驱动。由四组电路收集到的四组数据过多，他们在不同的时间内有效，这使得在稳定性消除和编码逻辑复杂化。在我们的TDC设计中，四个采样转移到在一个时钟域立即且只有一个边集检测的一个位模式，脉冲滤波器和计数锁存电路被使用。该稳定性在采样阶段才被限制，事实上，该稳定性在采样阶段没有任何损失，而是携带着输入信号的到达时间信息。解码在我们的设计中变得非常简单。详细的描述在第二节。在FPGA中的TDC

6、已经非常有用了。为费米实验室MIPP升级项目设计的TDC卡在论文中也有记载。 多采样结构可以有其他的应用。被熟知的“数字相位跟随”（DPF）的解串器电路也有记载。使用DPF，任何FPGA输入都可用于接收串行数据而无需专门的解串器，这些解串器只能由高端FPGA系列提供。该DPF可以补偿由于电缆温度的变化或者由于晶体振荡器发射机和接收机之间的频率差而造成的输入数据的相位漂移。2 TDC在FPGA中的运行在FPGA中的TDC是基于多相位时钟的。TDC的输入是通过四个寄存器被采样的，这些寄存器有四个相位的时钟。如图2所示。 图2 多抽样的TDC电路输入被缓冲，然后以同样的传播延迟发送到四个寄存器。这四

7、个寄存器连接到有90相位差的四个内部时钟上。0度和90度的时钟通过相锁回路（PLL）时钟合成器产生。他们的倒置用于产生180度和270度的时钟。根据到达时间，有关的输入逻辑电平转换被记录在不同地点的四个寄存器内。我们在Altera的Cyclone FPGA器件设备（EP1C6Q240C6）使用的时钟频率是360兆赫，它提供了0.69纳秒（LSB）的时间分辨率。一个单相的时钟域转移出现在第二和第三个记录层。然后输入信号的到达时间是编码为两个时间位（T0和T1）和一个数据有效信号（DV），计数器提供了一个命令时位。过渡边缘检测和脉冲滤波逻辑都包含在编码器内。对于许多应用程序，一个简单的领先优势编码

8、就足够了。例如在一些应用中，从一电线室估计输入脉冲，前缘和后缘都可以数字化。在这种情况下，一个额外的输出显示边缘的类型可能会需要。该脉冲滤波功能可以防止输入电路铃声由于被错误数字化而造成的超短脉冲。我们设计到连续四个位的位量子点至Q3模式使用了通过查找表的FPGA逻辑单元，以确定一个采样点是否在一个完善的脉冲边缘。回想一下使用查找表的FPGA，它可以实现“任何“四个输入的组合逻辑，满足边缘检测和脉冲过滤的应用要求。时序关键的信号通路通过设置输入缓冲区来控制，多采样寄存器和FPGA的内部时钟域转移寄存器如图3所示。这种对称的布局，保证从输入缓冲区到采样寄存器的一致的传播延迟，从而获得均匀的位宽，

9、最大限度地减少微分非线性。图3 FPGA中的时序关键路径 逻辑元件布局由“手动“的电子数据表完成。所有的TDC通道（每通道约10项）在输入缓冲区和触发器的位置都被保存在电子表格。在Cyclone FPGA器件中，四个通道都被集中在五个逻辑阵列块（LAB）里，如上面所示。设计者可能会进一步安排好每一个4通道组的位置去不断调整从输入引脚的输入延迟组，便于使不同群体的倾斜通道的最小化。试算表是编码到输出一个ASCII的文件，这个文件粘贴到为Quartus II与Altera FPGA设计软件的编制的指定文件中。 3 基于FPGA的模数转换器测试结果FPGA的ADC的几次试验已经完成，如图1所示电路。

10、具有两个值集的R1，R2和C来实现斜坡参考电压不同的时间常数。A、 线性参考电压拟在第一次配置，R1的值为50欧姆，R2为100欧姆，C =1000pF。FPGA用切换率为11.25 MHz，3.3V的差分电压驱动RC网络。该参考电压几乎是一个没有太多指数功能的三角波。输入到ADC的电压和参考电压的示波器的波形如图4所示。ADC的输入是四个不同宽度和峰值振幅的脉冲序列。图4 ADC输入（蓝色）输入和参考电压（黑色）输入信号是由参考电压每88ns在两次开头和结尾的坡道和每一次穿过坡道创建的一个由TDC数字化的翻转边缘。采样率大约是每秒采样22.5兆，（虽然前端和后斜采样点的采样间隔是不一样的）。

11、转换时期前端和后斜道的采样是由6位的测量范围的TDC来数字化的。 TDC的原始数据都显示在图5（a）中。转换时间进一步转化为输入电压的水平，如图5（b）所示。图5 （a）TDC的原始数据 (b)数字化波形应当指出，TDC的值不仅仅代表着采样点的电压水平，而且还代表着采样时间。在高精度应用中，采样时间的分歧应该予以考虑，但这不是太困难的事。B、指数参考电压 RC网络的放电性能指数，可用于提高ADC的动态范围。在第二个配置中，R1的值为50欧姆，R2为100欧姆，电容C为150pF。参考电压如图6所示，它有一个很短的时间常数。图6 参考电压的放电性能指数该指数样本的输入参考电压波形如图7（a）所示

12、。（请注意，图6和图7（a）的示波器时间尺度不同，但它们的电压表是相同的。）由图7（b）可以看出，一个平滑的波形通过尾随的坡道被数字化了。该测试展示了一个以22.5兆每秒的采样速率的6位的测量范围，而样本的尾部坡道动态范围大约是8位。图7 （a）输入波形（b）数字化波形被动元件被选择为下一代网络的参考电压斜坡，主要是为了简单。被动的RC网络的斜坡电压在本质上是非线性，这在有时被认为是一种缺陷。然而，在FPGA种，纠正非线性仅仅是通过查表来进行变换的。在我们的例子中，指数电压斜坡可进一步用于增加测量的动态范围，这已经成为一种优势。 在许多应用中，测量时只需要相对精度，也就是说，精细测量只应用在小

13、信号中，而对大信号来说，粗精度的测量已经足够了。4 总结研究了基于TDC的多采样，实施了低成本FPGA和测试台的三个应用：仅TDC下的多通道的FPGA， 仅在 ADC下的FPGA和一个解串器“数字相位跟随器”的讨论。FPGA接口直接与连续变量（抵达时间和输入电压）相接，单TDC的多通道FPGA， 单 ADC的FPGA和一个解串器“数字相位跟随器” 三个应用正在讨论中。FPGA与连续变量（抵达时间和输入电压）直接相接，可以消除外部设备，并简化系统设计。这种测量的实现可立即在FPGA中处理，而无需通过总线上的数据。The Design of Digital Signal Generator Bas

14、ed on FPGA Signal sources with high accuracy and operational frequency are used in the field of research and application of modern electronic measuring technology. Digital signal represent the development with it being one of the most widely measuring technology in the field. With the development of

15、 FPGA in a large scale and the maturing of SOPC, design technology have provided theoretical basis and technology support for the design and realization of such signal generators. This design of digital signal generator for FPGA as the core, with the FPGA as to achieve the frequency, phase, preset a

16、nd step, and complete the signal frequency and phase display. As used in the design of direct digital synthesis(DDS). Technology and effectively extends the use of FPGA output waveform of the frequency range to achieve the output of two-way high-precision phase of the sinusoidal signal, so that the

17、system is stable and reliable. With EDA software for the system, using VHDL language, to meet the CNC system for machining higher demands. Experimental results show that the original part of the CNC system compared to the control circuit design using EDA technology makes the NC signal generator syst

18、em with higher reliable, real-time, high operation speed and high integration. At the same time as EDA technology with in-system programmable FPGA chip feature, so the shift key signal generator is designed to change the same as the software, which brings the system to facilitate maintenance. Combin

19、ed with FPGA to extend effectively the frequency range of theoutput waveform to achieve the output of two-way high-precision phase of the sinusoidal signal, so that the system is stable and reliable. Keywords: signal generator; DDS; System On a Programmable Chip; The FPGAI. INTRODUCTIONFPGA is a dig

20、ital device. However, with suitable use of the FPGA resources, it is possible to use FPGA to digitize multi-channel analog waveforms. The digitized waveforms can be directly processes in the FPGA. There are several possible schemes of digitizing analog signals. One of the schemes we used in our FPGA

21、 ADC study is based on the ramping-comparing approach as shown in Fig.1.The analog inputs are directly connected to the FPGA input pins. A passive RC network is connected to the FPGA output pins so that a periodic reference voltage ramp can be generated. The differential input buffers are used as co

22、mparators to generate logic transitions inside the FPGA when the reference voltage ramps across the input voltage levels. The transition times are digitized by the TDC block implemented in the FPGA. Since the period, the RC network parameters and the starting time of the ramps are known the input vo

23、ltage levels can be derived from the transition times.In todays FPGA devices, differential input buffers are good comparators within a sufficiently large range of input voltage levels, since they are designed to be compatible with various signaling standards. Many comparator-based ADC schemes can be

24、 implemented with FPGA. For example, with the delta-sigma scheme. the signal can be tracked promptly yielding smaller digitization errors at a cost of higher FPGA resource usage (typically, 4 I/O pins per channel). With Wilkinson rundown scheme, charge integration of narrow pulse can be combined wit

25、h the digitization, although more external analog circuits are needed. The ramping comparing scheme we studied here (or single-slope ADC based on classification in Reference, although both ramping slopes can be utilized) is a suitable choice for applications with large channel count of relatively sl

26、ow signals. (In some references, the single-slope scheme is mistakenly referred as Wilkinson ADC that is based on dual -slope principle.)A key functional block, Time-to-Digit-Converter (TDC) is needed in FPGA. There are two TDC schemes that can be implemented in FPGA: delay chain scheme and multisam

27、pling scheme . The TDC we used in this work is multisampling scheme with quad clock as in Reference . In Reference , four sets of sample, edge detect, pulse filter and count latch are driven by four clocks with 90o phase separations. These four sets of data collected by four sets of circuits are exc

28、essive and they become valid at different time, which makes the meta-stability elimination and encoding logic complicate. In our TDC design, the four samples are transferred into a bit pattern in a single clock domain immediately and only one set of edge detect, pulse filter and count latch circuit

29、is used. The meta-stability is limited at the sampling stage only and in fact, the meta-stability in sampling stage does no harm but carrying the input signal arrival time information. The decoding becomes very simple in our design. The detail is described in Section II.The TDC in FPGA alone is alre

30、ady very useful. The TDC card designed for Fermilab MIPP upgrade project is documented in this paper.The multi-sampling structure can have other applications. A deserializer circuit known as “Digital Phase Follower” (DPF) is also documented. Using DPF, any FPGA input can be used to receive serial da

31、ta without needing dedicated deserializer that is only available in high-end FPGA families. The DPF can compensate input data phase drift not only due to cable temperature variation, but also due to crystal oscillator frequency difference between transmitter and receiver.II. TDC IMPLEMENTED IN FPGAT

32、he TDC inside the FPGA is based on multi-phased clock. The input of the TDC is sampled by four registers with four phases of the clock as shown in Fig. 2.The input is buffered, and then sent to four registers with equal propagation delays. The four registers are connected to four internal clocks eac

33、h with 90o phase difference. The 0o and 90o clocks are generated by the phase-lock-loop (PLL) clock synthesizer and their inversions are used for 180o and 270o clocks. Depending on arrival time, the transitions of the input logic levels are recorded at different locations within the four registers.

34、The clock frequency used in our Altera Cyclone FPGA device (EP1C6Q240C6) is 360 MHz, which provides a time resolution of 0.69 ns (LSB). A transfer to a single phase clock domain occurs in the second and third register layers. Then the arrival time of input signal is encoded into two time bits (T0 an

35、d T1) and a data valid signal (DV). A counter provides the upper order time bits.Transition edge detection and pulse filtering logics are included in the encoder. For many applications, a simple leading edge encoding is sufficient. In some applications, for example, to estimate input pulse charge fr

36、om a wire chamber, both leading and trailing edges may be digitized. An additional output indicating the type of edge may be needed in this case. The function of pulse filtering prevents ultra short pulses due to input circuit ringing from being mistakenly digitized. In our design up to four consecu

37、tive bits in the bit pattern QD to Q3 are used by a look-up table in FPGA logic element to determine if a sampling point is at the edge of a well established pulse. Recall that the using a look-up table in FPGA, one can implement “any” four-input combinational logic, satisfying the edge detection an

38、d pulse filtering requirements of an application.Timing critical signal paths are controlled by placing the input buffer, multi-sampling registers and clock domain transfer registers in the FPGA as shown in Fig. 3. This symmetric placement assures equal propagation delays from input buffer to the sa

39、mpling registers, resulting in uniform bit widths and thus minimizes differential non-linearity.The logic element layout is done “manually” with a spread sheet. The locations of the input buffer and flip-flops, (about 10 items per channel) for all TDC channels are kept in the spread sheet. In Cyclon

40、e FPGA devices, four channels are grouped together in five logic array blocks (LAB) as shown above. The designer may further arrange the location of each four-channel group to adjust the input delay from input pin to the group so that the skews between different channel groups are minimized. The spr

41、ead sheet is coded to output an ASCII file that is pasted into the assignment file for compilation with the Quartus II Altera FPGA design software.III. TEST RESULTS OF FPGA BASED ADCSeveral tests of FPGA ADC are done with circuits shown in Fig. 1 with two sets of values of R1, R2 and C to achieve di

42、fferent time constants for the ramping reference voltage.A. Quasi-linear Reference VoltageIn the first configuration, the values of R1 = 50, R2 = 100 and C = 1000pF. The FPGA drives the RC network with a toggling rate of 11.25 MHz in differential 3.3V level. The reference voltage is nearly a triangl

43、e wave with not much exponential feature. The oscilloscope traces of the input voltage to the ADC and the reference voltage are shown in Fig. 4. The input to ADC is a sequence of four pulses with different widths and peak amplitudes.The input signal is crossed by the reference voltage twice every 88

44、ns by both leading and trailing ramps and each crossing creates a flipping edge that is digitized by the TDC. The sampling rate is approximately 22.5 M samples/sec, (although the sampling intervals between the points sampled by the leading and trailing ramps are not the same). The transition times s

45、ampled by both the leading and trailing ramps are digitized by the TDC with 6-bit measurement range. The raw TDC data are shown in Fig. 5(a). The transition times are further converted to input voltage levels in natural unit as plotted in Fig. 5(b).It should be pointed out that the TDC values repres

46、ent not only the voltage levels at the sampling points, but also the sampling times. In high precision applications, the differences of the sampling times should be taken into account but it is not too difficult to do so.B. Exponential Reference VoltageThe exponential discharge property of the RC ne

47、tworks can be used to increase the dynamic range of the ADC. In the second configuration, the values of R1 = 50, R2 = 100 and C = 150pF. The reference voltage shown in Fig. 6 has a short time constant.The exponential reference voltage samples the input waveform shown in Fig. 7(a). (Note that the osc

48、illoscope time scales for Fig. 6 and 7(a) are different but the voltage scales are them same.) It can be seen from Fig. 7(b) that a smoother waveform is digitized by the trailing ramp. This test shows a 6- bit measurement range at 22.5 M samples/sec while the dynamic range of the trailing ramp sampl

49、es is approximately 8 bits.Passive components are chosen for the ramping reference voltage generation network primarily for simplicity. The ramping voltage from passive RC network is intrinsically nonlinear which sometimes is viewed as a disadvantage. In FPGA, however, correcting nonlinearity is mer

50、ely a transform via a look-up table. In our example here, the exponential voltage ramp can be further used to increase measurement dynamic range, which becomes an advantage.In many applications, only relative precision in a measurement is needed, i.e., finer measurements are only needed for small si

51、gnals while for larger signals, coarser measurements are sufficient.IV. CONCLUSIONMulti-sampling based TDC has been studied, implemented in low cost FPGA and bench tested.Three applications: multi-channel FPGA-only TDC, FPGA only ADC and a deserializer “Digital Phase Follower” are discussed. Interfa

52、cing FPGA directly with the continuous variables (arrival time and input voltage) eliminates external devices and simplifies system design. The measurement made can be processed immediately in the FPGA without having to pass data via on board busses.REFERENCES1 P. Allen & D. Holberg, CMOS Analog Cir

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