16位模型机的设计

《16位模型机的设计》由会员分享，可在线阅读，更多相关《16位模型机的设计（15页珍藏版）》请在装配图网上搜索。

1、 16位CPU的设计要求：此模型机的功能是将存储区的数据块复制到另一个存储区。汇编代码如下：START：LOADI R1，0010H ;源操作数地址送R1LOADI R2，0030H ；目的操作数地址送R2LOADI R6，002FH ；结束地址送R6NEXT：LOAD R3，R1 ；取数STORE R2，R3 ；存数BRANCHGTI START ；如果R1R6，则转向STARTINC R1 ；修改源地址INC R2 ；修改目的地址BRANCHI NEXT ；转向NEXT1. 16位CPU的组成结构2. 指令系统的设计一、 指令格式1) 单字指令格式2) 双字指令格式二、 指令操作码操作码指

2、令功能00001LOAD装载数据到寄存器00010STORE将寄存器的数据存入到存储器00100LOADI将立即数装入到寄存器00101BRANCHI无条件转移到由立即数指定的地址00110BRANCHGTI如果源寄存器内容大于目的寄存器的内容，则转移到由立即数指定的地址00111INC寄存器内容加1指令依据以上设计的指令系统，则完成数据块复制的程序如下：地址机器码指令 功能说明0000H0001H2001H0010HLOADI R1，0010H源操作数地址送R10002H0003H2002H0030HLOADI R2，0030H目的操作数地址送R20004H0005H2006H002FHLO

3、ADI R6，002FH结束地址送R60006H080BHLOAD R3，R1取数0007H101AHSTORE R2，R3存数0008H 0009H300EH0000HBRANCHGTI 0000如果R1大于R6，则转向地址0000000AH3801HINC R1修改源地址000BH3802HINC R2修改目的地址000CH000DH2800H0006HBRANCHI 0006H转向00006H，实现循环3. VHDL设计一、 程序包：说明运算器的功能、移动寄存器的操作、比较器的比较类型和用于CPU控制的状态类型。library ieee;use ieee.std_logic_1164.a

4、ll;use ieee.std_logic_arith.all;package cpu_lib is subtype t_shift is unsigned (3 downto 0);constant shftpass :unsigned(3 downto 0):=0000;constant sftl :unsigned(3 downto 0):=0001;constant sftr:unsigned(3 downto 0):=0010;constant rotl :unsigned(3 downto 0):=0011;constant rotr :unsigned(3 downto 0):=

5、0100;subtype t_alu is unsigned(3 downto 0);constant alupass :unsigned(3 downto 0):=0000;constant andOp :unsigned(3 downto 0):=0001;constant orOp:unsigned(3 downto 0):=0010;constant notOp :unsigned(3 downto 0):=0011;constant xorOp :unsigned(3 downto 0):=0100;constant plus :unsigned(3 downto 0):=0101;

6、constant alusub :unsigned(3 downto 0):=0110;constant inc :unsigned(3 downto 0):=0111;constant dec :unsigned(3 downto 0):=1000;constant zero:unsigned(3 downto 0):=1001;subtype t_p is unsigned 2 downto 0);constant eq :unsigned(2 downto 0):=000;constant neq :unsigned(2 downto 0):=001;constant gt:unsign

7、ed(2 downto 0):=010;constant gte :unsigned(2 downto 0):=011;constant lt :unsigned(2 downto 0):=100;constant lte :unsigned(2 downto 0):=101;subtype t_reg is std_logic_vector(2 downto 0);type state is (reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,load2,load3,load4,store2,store

8、3,store4,move2,move3,move4,incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,loadI2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);subtype bit16 is std_logic_vector(15 downto 0);end cpu_lib;二、基本部件

9、的设计1) 运算器的设计 功能library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity alu is port(a,b:in bit16;sel:in t_alu;c:out bit16);end alu;architecture rt1 of alu is beginprocess(a,b,sel)begincase sel iswhen alupass= c c c c c c c c c c c if a=b then pout =1 after

10、 1ns;else pout if a/=b then pout =1 after 1ns;else pout if ab then pout =1 after 1ns;else pout if a=b then pout =1 after 1ns;else pout if ab then pout =1 after 1ns;else pout if a=b then pout =1 after 1ns;else pout pout y y y y y y=0000000000000000 after 1 ns;end case;end process;end rt1;4) 寄存器librar

11、y ieee;use ieee.std_logic_1164.all;use work.cpu_lib.all;entity reg is port(a:in bit16;clk:in std_logic;q:out bit16);end reg;architecture rt1 of reg isbeginprocessbeginwait until clkevent and clk=1;q=a after 1ns;end process;end rt1;5) 寄存器组library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_un

12、signed.all;use work.cpu_lib.all;entity regarray is port(data:in bit16;sel:in t_reg;en,clk:in std_logic;q:out bit16);end regarray;architecture rt1 of regarray is type t_ram is array (0 to 7) of bit16;signal temp_data:bit16;beginprocess(clk,sel)variable ramdata:t_ram;beginif clkevent and clk=1 then ra

13、mdata(conv_integer(sel):=data;end if;temp_data=ramdata(conv_integer(sel) after 1 ns;end process;process(en,temp_data)beginif en=1 then q=temp_data after 1 ns; else q=ZZZZZZZZZZZZZZZZ after 1 ns;end if;end process;end rt1;6) 三态寄存器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.al

14、l;use work.cpu_lib.all;entity trireg isport(a:in bit16;en,clk:in std_logic;q:out bit16);end trireg;architecture rt1 of trireg issignal val:bit16;beginprocessbeginwait until clkevent and clk=1;val=a;end process;process(en,val)beginif en=1 then q=val after 1 ns;elsif en=0 then q=ZZZZZZZZZZZZZZZZ after

15、 1 ns;else q=XXXXXXXXXXXXXXXX after 1 ns;end if;end process;end rt1;7) 控制器采用状态机实现library IEEE;use IEEE.std_logic_1164.all;use work.cpu_lib.all;entity control isport( clock,reset,pout:in std_logic; instrReg:in bit16;progtrWr,progtrRd,addrRegWr,outRegWr,outRegRd:out std_logic;shiftSel:out t_shift; alu

16、Sel:out t_alu; pSel:out t_p;opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:out std_logic;regSel:out t_reg );end control;architecture rtl of control issignal current_state, next_state : state;beginprocess( current_state, instrReg, pout)beginprogtrWr = 0; progtrRd = 0; addrRegWr = 0; outRegWr = 0;outRegRd

17、 = 0; shiftSel = shftpass; aluSel = alupass; pSel = eq;opRegRd = 0; opRegWr = 0; instrWr = 0; regSel = 000;regRd = 0; regWr = 0; rw = 0; vma aluSel=zero after 1 ns; shiftSel=shftpass; next_state aluSel=zero; shiftSel=shftpass; outRegWr=1; next_state outRegRd=1; next_state outRegRd=1; progtrWr=1;addr

18、RegWr=1; next_state vma=1; rw = 0; next_state vma=1; rw=0;instrWr=1; next_state case instrReg(15 downto 11) iswhen 00000 = next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1;next_state regSel=instrReg(5 downto 3); regRd=1; aluSel=alupass;shiftSel=shftpass

19、; next_state progtrRd=1; alusel=inc; shiftsel=shftpass;next_state progtrRd=1; alusel=inc; shiftsel=shftpass;next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1; alusel=inc;shiftsel=shftpass; next_statenext_state regSel = instrReg(5 downto 3); regRd = 1;add

20、rregWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; regSel = instrReg(2 downto 0);regWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1;addrregWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;next_state regSel = instrReg(5 downto 3); regRd = 1; rw = 1; next_state

21、regSel = instrReg(5 downto 3); regRd = 1;aluSel =alupass;shiftsel = shftpass; outRegWr = 1; next_state outRegRd = 1; next_state outRegRd = 1;regSel = instrReg(2 downto 0); regWr = 1; next_state progtrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd

22、 = 1; progtrWr=1; addrregWr=1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;regSel = instrReg(2 downto 0);regWr = 1; next_state progtrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd=1; progtrWr=1; addrregWr=1;next_state vma=1; rw=0; next_

23、state vma = 1; rw = 0;progtrWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;opRegWr = 1; next_state opRegRd = 1; regSel = instrReg(2 downto 0);regRd = 1; psel = gt; next_state opRegRd = 1 after 1 ns;regSel = instrReg(2 downto 0); regRd = 1; psel = gt;if pout = 1 then next_state = bgtI5;e

24、lse next_state progtrRd=1; alusel=inc; shiftSel=shftpass;next_state progtrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd = 1;progtrWr = 1; addrregWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; progtrWr = 1; next_state regSel = in

25、strReg(2 downto 0); regRd = 1; alusel = inc;shiftsel = shftpass; outregWr = 1; next_state outregRd = 1; next_state outregRd = 1; regsel = instrReg(2 downto 0);regWr = 1; next_state progtrRd = 1; next_state progtrRd = 1; addrRegWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; instrWr =

26、 1; next_state progtrRd=1; alusel=inc; shiftsel=shftpass;next_state progtrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd=1; progtrWr=1;addrregWr=1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; instrWr = 1; next_state next_state = incPc

27、;end case;end process;process(clock, reset)beginif reset = 1 then current_state = reset1 after 1 ns;elsif clockevent and clock = 1then current_state = next_state after 1 ns; end if;end process;end rtl;8) 存储器的设计LPM_RAM定制首先，定制初始化数据文件，建立Memory Initialization File(.mif)文件，选择FileNew命令，并在New窗口选择Other file选项，再选择Memory Initialization File选项。内容如下：完成后，保存文件。之后，定制LPM_RAM。设计步骤如下：选择ToolsMegaWizard Plug-In Manager命令，打开MegaWizard Plug-In Manager 对话框，选中Create a new custom megafunction variation，单击Next，按提示选择RAM的控制线、地址线、数据线。一步步完成。4 顶层原理图的设计15 / 15