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1、毕业设计 (论文 )外文资料翻译系别：电子信息系专业：通信工程班级：B100309姓名：张杨学号：B外文出处：附件：1. 原文；2.译文2014 年 03 月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of itsmajor features for a developer new to the device.Future a

2、rticles will examineother aspects of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 1

3、6-bit instruction set, known as THUMB. This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle,other instructions such as data transfer instructions, are multi-cycle. To increase the performance of th

4、ese instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip embedded I

5、CE that allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer

6、instructions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages;

7、FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance.

8、As we shall see later the ARM 7 designers had some clever ideas to solve this problem.123456InstructionFetchDecodeExecuteFig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmers model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (

9、PC). Since the ARM 7 is a load-and-store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.Mov M1,R1M1M2Add R4,R1,R2 (R4=R0+R2)3Mov M2,R

10、2Mov R4,M3M3Fig 2 Load And Store ArchitectureAs stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions

11、 so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSHorPOP the entire register set onto the stack in a single instruction. R14 has special significance and is called the link register. When a call

12、is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 into R15, the PC. For multiple calling trees, the contents of R14 (the link register) must be placed onto the st

13、ack.R0R1R2R3R4R515 User registers +PCR6R7R8R9R10R11R12R13 is used as the stack pointerR13R14 is the link registerR14R14 is the Program CounterR15(PC)Current Program Status RegisterCPSRFig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR)

14、. This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSRcontains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing

15、 and enable/disable interrupts.31 30 29 28 27NZCVCondition code flagsNegativeCarryOverflow876543210MMMMMIFT43210Interrupt enableIRQOperating modeFIQFIQThumb instruction setIRQSystemUserUndefined instructionAbortFig 4 Current Program Status Register and FlagsException And Interrupt ModesThe ARM 7 arc

16、hitecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interrupt sources and their own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can

17、only be changed when an exception is generated.FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a systemIRQ: (Interrupt ReQuest) This supports all other interrupt sources in a systemSupervisor: A protected mode

18、for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after resetAbort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generatedUndefined Instruction: If a FETCHED opcode is not an ARM instruction, an undefined in

19、struction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Sta

20、ck pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一 the saved program status register (SPSR)，is added. When the processor changes the current value of the CPSR stored in the SPSR，this can be restored on exiting the excep

21、tion mode.System&UserFIQSupervisorAbortIRQUndefinedR0R0R0R0R0R0R1R1R1R1R1R1R2R2R2R2R2R2R3R3R3R3R3R3R4R4R4R4R4R4R5R5R5R5R5R5R6R6R6R6R6R6R7R7-fiqR7R7R7R7R8R8-fiqR8R8R8R8R9R9-fiqR9R9R9R9R10R10-fiqR10R10R10R10R11R11-fiqR11R11R11R11R12R12-fiqR12R12R12R12R13R13-fiqR13-svcR13-abtR13-irqR13-undR14R14-fiqR14

22、-svcR14-abtR14-irqR14-undR15(PC)R15(PC)R15(PC)R15(PC)R15(PC)R15(PC)CPSRCPSRCPSRCPSRCPSRCPSRSPSR-fiqSPSR-svcSPSR-abtSPSR-irqSPSR-undFig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct typ

23、es.(i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region.(iii) Exceptions

24、 unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, thecurrent value of the PC+4 is saved into the Link register (R14) of th

25、e privileged mode and the current value of CPSRis saved into the privileged modes SPSR.The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter is forced to the exception vector address and processing of the exception can

26、start. Usually the first action of the exception routine will be to push some or all of the user registers onto the stack.Exeption typeModeResetSupervisorUndefined instructionUndefinedSoftware interrupt (SWI)SupervisorPrefetch Abort(instruction fetch memoryAbortabort)Data Abort (data access momory a

27、bort)AbortIRQ (interrupt)IRQFIQ (fast interrupt)FIQMeaning 0x00000000 0x000000040x000000080x0000000C0x000000100x000000180x0000001CFig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM archit

28、ecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possible.Once

29、 processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR mustbe restored from the SPSR and finally the Program Counter is restored by movin

30、g the contents of the link register to R15, . the Program Counter). The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instruction set

31、has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format.ARM instructions typically have a three-operand format, as shown below ADD Rl，R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors there is a sm

32、all group of instructions that are conditionally executeddepending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.3128CONDFig. 7 Instruction Condition Code BitsThe top four bits of e

33、ach instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional branches of th

34、ree instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used.SuffixFlagsMeaningEQZ setequalNEZ clearnot equalCSC setUnsigned higher or sameCCC clearUnsigned lowerMIV setnegativePLN clearPositive or zeroVSV setoverflowV

35、CV clearno overflowHIC set and Z clearunsigned higherLSC clear and Z setunsigned lower or sameGEN equals Vgreater or euqalLTN not equal to Vless thanGTZ clear AND (N equals V)greater thanLEZ set OR (N not equal to V)less thanAL(ignored)greater thanFig. 8 Instruction Condition CodesThus our ADD instr

36、uction below could be prefixed with a condition code, as shown. This adds no overhead to instruction executionEQADD R1，R2，R3 ;If(Zero flag = 1)then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. Th

37、is takes place in the same cycle as the instruction. The ADD instruction could be expanded as followsEQADD R1，R2 R3，LSL #2 ; If ( Zero flag = 1) then R1 = R2+ (R3 x 4) Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1，R2 R3，LSL #2; c

38、ondition code flagsIf (Zero flag = 1) then R1 = R2 + (R3 x4)and setIn the ARM instruction set there are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions.The standard branch (B) instruction allows a jump of around+-32Mb. A co

39、nditionalbranch can be formed by use of the condition codes. For example, a branch not equal would be the branching instruction B and the condition code NE for not equal giving BNE. The next form of the branch instruction is the branch with link.This is the branch instruction but the current value o

40、f the PC +4 is saved into R14, the link register. This acts as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on

41、 the type of exception, it may be necessary to modify the contents ofthe link register to get the correct return address. For example, in the case of an IRQor FIQ interrupt, the processor will finish its current instruction, increment the PC tothe next instruction and then jumping to the vector tabl

42、e. This means that the valuein the link register is PC+4 or one instruction ahead of the return address. This meanswe need to subtract 4 from the value in the link register to get the correct returnaddress.This can be done in a single instruction thus:SUBSpc,r14,B 0x80000x400PC=0x8000LDA R2,#100x800

43、0BL 0x80000x400PC=0x8000R14=0x400+4LDA R2 ,#100x8000#4Both thebranch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb instructions. Branch link exchange will jump to a

44、 location, save PC+4 into the linkregister and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processing.BLX 0x80000x400PC=0x8000Y=1R14=0x400+40x8000L

45、DA R2,#10BLX 0x80000x400PC=0x8000T=1R14=0x400+40x8000LDA R2 ,#10Fig. 10 Branch Exchange and Branch Link Exchange Instruction Operation Software InterruptsThe ARM instruction set has a software interrupt instruction. Execution of this instruction forces an exception as described above; the processor

46、will enter supervisor mode and jump to the SWI vector at 0x00000008.3128 2724 23Cond1111OrdinalFig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal.On execution of an SWI instruction, this ordinal can be examined to determine whi

47、chSWI procedure to run and gives over 16 million possible SWI functions.Swi_ #1 . call swi function oneTn the swi handlerregister unsigned*link ptr asm (r14) In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are the running in a supervisor mode, w

48、ith a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM 7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless t

49、o say, this is extremely useful when entering or exiting a procedure.R6STMM0R15LDMMx=16Fig. 12 Load and Store Multiple Instruction OperationThe CPSRand SPSRare only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.M

50、SRR0CSPRSPSRR15MRSR0CSPRSPSRR15Fig. 13 Programming The SPSR And CPSR Registers THUMB SupportThe ARM processor is capable of executing both 32-bit (ARM) instructions and 16- Bit (Thumb instructions). The Thumb instruction set must always be entered by running a Branch exchange or branch link exchange

51、 instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they are unconditionally executed except though for branch instructions.16 bitInstructionARMThumbThumbPipelineInstructioncodeDecompressorDecode

52、rFig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一 Rl5. A instructions can access the full register set.R0R1R2R3R4Low RegistersR5R6R7R8R9R10R11High ResigtersRestricted AccessR12R13CPSRR14R15Thumb programmers modelThe Thumb

53、 instruction set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except t

54、hat the ordinal field is only8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSRis restored the, Thumb bit will be reset and the processor continues to run Thum

55、b instructions.ResetARMBCXTHUMBexeptionsARMEnd of exeptionsTHUMBBXARMThumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you o

56、nly have 16-bit wide memory then Thumb code will be faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7 的体系结构介绍特里沃马丁曾，鼠技术总监本文给出了 ARM 7 架构的概述和开发新的设备，以及主要功能的描述，未来将研究 ARM 体系结构的其他方面。基本特点ARM7 单片机原理的特点是， 它是一个基于寄存器的加载和存储与

57、多个操作模式的体系结构。 ARM7 是一个 32 位单片机，它也能够运行 16 位指令集，被称为 “拇指 ”。 这有助于实现一个更大的代码密度和加强节能。 而所有的寄存器到寄存器的数据处理的指令都是单周期指令， 如数据传送指令， 多周期。增加这些指令的性能， ARM7 具有三级管道。由于与低门数设计的固有的简单性， ARM7 的低功耗处理在瓦 / MIP 基础行业是领导者。最后，以协助开发， ARM 内核有一个内置的 JTAG调试端口和芯片上的 “嵌入式冰 ”，允许程序被下载和全面调试系统。为了保持 ARM 既简单又划算，代码和数据区域通过单数据总线访问。 因此 ARM7 能够单循环执行所有的

58、数据处理指令， 数据传送指令可能需要几个周期， 因为他们将需要至少两个访问总线（一个是指令一个是数据）。为了提高性能，三个管道被用于允许多个指令同时处理。这个管道有三个阶段：接收，编译，执行。每一个阶段的硬件设计是独立的， 三个指令能够同时地被执行。 在迅速上升的连续代码中，此管道是最有效的。 然而一个分支指令会导致管道的性能被破坏。 我们必须看到后来的 ARM7 设计师提出一些聪明的办法来解决这些事情。123456指令送达译码执行图 1ARM7 的三个阶段管道ARM 7 程序设计模型程序设计员的 ARM7 模型由 15 个用户寄存器组成，如图 3 所示， R15 被用做为程序设计器，自从 A

59、RM7 作为下载和存储建筑学以后，用户程序必须从 CPU暂存器下载数据， 执行的数据和存储的结果返回到寄存器， 不像其他的处理器没有记忆存储器指令可用。M1Mov M 1,R1Add R4,R1,R2 (R4=R0+R2)3Mov M 2,R2M2Mov R4,M3M3图 2 下载和存储体系结构如上所述， R15 是程序计数器。 R13 和 R14 也有特殊功能： R13 是被用作堆栈指针，尽管它仅仅被定义作为规划会议。不寻常的ARM7 指令集没有 push 和 pop指令，所以堆栈处理是通过一组指令,允许下载和在一个单一的操作多个寄存器存储，因此它可能是在整个寄存器组中push 和 pop 堆栈上的一个单寄存器。 R14具有特殊的意义，叫做 “环节注册 ”。当访问到达程序时，返回地址自动的放入R14，而不是放入堆栈，正如所料。然后返回