ASIC与大型逻辑设计实习课.

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1、ASIC?Pq?T?剎-pftatasheetmax 全面 快速 免费的数据表査询服务 1(2?oCBIC & ModelSimAgendau Cell Base IC Design u ModelSimu Libraryu Projectu VHDL Compiler & Simulation u Simulation Windows u Tutorial u LabCiKiJlt tMi De冲x)csign Format VHDl Verily System designV HDL VcnkigTcclinolugj DependentV HDLA cnloi LDIJ|4*4ii nM

2、odelSimModelSimftatasheetmax 全面 快速 免喪的数据喪査询银务 LibraryRege nerate your libraryu Regenerate your design libraries with -refresh.u Use the vcom compiler with the -refresh option to update the VHDL design units in libraryu Use vlog with the -refresh option to update Verilog design unitsvcom -work mylib

3、-refreshvlog -work mylib -refreshDesig n library contentsu A design library is a directory that serves as a repository for compiled design units. The design units contained in a design library consist of VHDL entities, packages, architectures, and con figurati ons; and Verilog modules and UDPs (user

4、 defi ned primitives). The design units are classed as follows:?Primary desig n un itsConsist of entities, package declarations, configuration declarations, modules, and UDPs. Primary design units within a given library must have unique names.?Sec on dary desig n un itsCon sist of architecture bodie

5、s and package bodies. Secon dary desig n un its are associated with a primary desig n un it. Architectures by theftatasheetmax 全面 快速 免费的数据表査询银务 same n ame can exist if they are associated with differe nt en tities.Desig n library typesu working librariesA working library is the library into which a

6、design unit is placed after compilation. u resource libraries.A resource library contains design units that can be refereneed within the design unit being compiled.?The library named work is predefined in the compiler and need not be declared explicitly.?workis also the library n ame used by the com

7、piler as the defaultdestination of compiled design units. In other words the work library is the working library.(atasheetmax 全面 快速 免费的数据裘査询赧畀 Creati ng a new libraryModelSIm SE/EE 5.4cyiew Bum msoio options 翌fneov/甲 Model T 000# - Loadir# - - leadir# - Compi CompiRrov駡& Lltirafies.-lodalbiiTrdesign

8、Creale a Nevj Lrl)rafyView Library COnlents . FPGA Library Majnaer .Compile.C. jvfjiie Erojednt 34C Compiler 000 OE Jul Z3 2Load Design.End Simulatbn.Creati ng a worki ng library from the comma nd line !vlib u Creati ng a worki ng library with the graphic in terface !Desig n Create a New LibraryCrea

9、ti ng a new libraryQatasheetmax 全面 快速 免费的数据表査询银务 u Create?a new library and a logical mapping to itType the new library name into the Library field. This creates a library sub-directory in your curre nt worki ng directory, i nitially mapped toitself. ?a new library only (no mapp ing)Type the new lib

10、rary name into the Library field. This creates a library sub-directory in your current working directory.?a map to an existi ng libraryType the new library n ame into the Library field, the n type in to the Maps to field or Browse to select a library n ame for the mapp ing.Viewi ng and deleti ng lib

11、rary contentsu Viewi ng and delet ing library contents from the comma nd line !vdir -lib !vdel -lib u Viewing andthe graphic in terface!Desig n ViewLibrary ContentsAssig ning a logical n ame to a desig n libraryuLibrary mapp ings with the GUI!Desig n Browse Libraries ?AddCreate a new lib.?EditModify

12、 the logicallibrary n ame and thepath name to which it is mapped.ModelSim(aatasheetmaxwww.d ata 全面 快速 免费的数据裘査询赧务 ProjectWhat is a project?u A project is a collect ion en tity for an HDL desig n un der specificati on or test. At a minim um, it has a root directory, a work library and sessi on state w

13、hich is stored in a .mpf file located in theproject s root directory. A project mayo consist of:?HDL source files?subdirectories?local libraries?refere nces to global librariesINI and MPF file?A .in i file specifies in itial tool sett in gs a nd is fully supported outside of a project.?By convention

14、 the new project files will have a .mpf extension.?A .mpf project file is specific to a given work session and may include the settings from a .in i file.?A .mpf project file is located in the project worki ng directory. This en sures that the path to a .mpf file will be /vproject_ name/vproject_ na

15、me.mpf?A .mpf project file may be updated with curre nt tool sett in gs, whereas a .in i file is used for in itial tool defaults. A .mpf project file also maintains cha nges to project sett in gs. Project operatio nsu Create: File New New Project?New -Inherit default settings from the current .ini f

16、ile (must specifyproject n ame and worki ng directory). Creates a fresh project file. Opens the new project. ?Copy-Use an existi ng project, but cha nge the work ing directory.Copies all dependent files/libraries that are specified relativeto the working directory. Absolute library paths are unchang

17、ed in the copied project file. Opens the new project. u Open: File Open Open Project?Ope n an existi ngproject (cha nge worki ng directory, read sett ings from project file).ftatasheetmax全面 快速 免费的数据表查询服务StuLibrary IEEK.匚 IEZE td_logic_1164 iLLpIentity OFF ist (elk, D LJl 8td lolE .0oot iit3Mlai|LcJ

18、申tj n： DFF.1011IE7irclntct2c* Ka of i)rr isjb.gijhseqfO f厂厂厂？r bguiWorki ng with a Project(iatasheetmax 全面 快速 免费的数据喪査询眾务 u Opening a project!File Open Open Project?Create HDL source files!File New New Source?lmport HDL source files!File New Import SourceWorking with a Project u Compiling a project!D

19、esig n Compile ProjectuSimulati ng a projectDesig n Load New Desig nModelSimOatasheetmax全面 快速 免發的数据表査询淼务VHDL Simulation(Jatasheetmax 全面 快速 免费的数据表査询服务 Sett ing default compile opti ons!Optio ns Compile?Use 1993 Ian guage syntaxSpecifies the use of VHDL93duri ng compilati on. The 1987sta ndard is the

20、default. Same asthe -93 switch for the vcomcomma nd?VHDL93You can make the VHDL93 standard the default by including the following line in theINI file:(atasheetmax 全面 快速 免喪的数据喪査询激务 Setting default compile optionsu Flag Warnings on?Unbound Comp onentFlags any comp onent in sta ntiati on in the VHDL so

21、urce code thathas no matchi ng enti in a library that is refere need in the source code, either directly or in directly. ?Process without a wait stateme ntFlags any process that does not contain a wait stateme nt or a sen sityvlist. ?Null RangeFlags any null ran ge, such as 0 dow n to 4.?No space in

22、 time literal (e.g. 5ns)Flags any time literal that is missing a space between the number and the time unit. ?Multiple drivers on un resolved sig nalFlags any un resolved sig nals that have multiple drivers.Setting default compile optionsu Check for?Sy nthesisTurns on limited syn thesis-rule complia

23、 nee check ing?VITAL (VHDLI nitiativeTowardASICLibraries) Complia neeToggle VITAL complia nee check ingu Optimize for?StdLogic1164Causes the compiler to perform special optimizati ons for speed ing up simulatio n whe n the multi-value logic package std_logic_1164 is used. Uni ess you have modified t

24、he std_logic_1164 package, thisopti on should always be checked?VITALToggle accelerati on of the VITAL packagesSimulati ng with the graphic in terface!二 1Load DesignF|rLoadSave 5etung&.CancelLSknulate:AddDesign Load New Designu Options/Simulator Resoluti on?Library?Smulateven tity ()1. Type a design

25、 unit name (configuration, module, or entity) into the field, separateadditi onal n ames with a space. Specify library/desig n un its withthe follow ing syn tax:.2. Click on a n ame in the Desig n Unit list below and click the Add butt on.Leave this field blank and click on a name in the Design Unit

26、 list (single unit only).Setting default simulation options!Options Simulation. ModelSimSimulatio n Win dowsALP -Vi! * - !J -I-S-HiJiM-I fIti, Im3ik Dili il - Z1iEEEfiLif 1EES jEEirr !srr ui_v,lxql=.讥-|ij IrariFjET JLHw3Tirtm Jid亦H rwn，2WhiWin dows overviewEile WindowdataflowI /cordic tb/line 50/cor

27、dic_tb/u1 /de/cordic tfa/uVdOI/cordicJb/uUdl/cordic tb/u1/d2一/cardie tb/u1/d.3-/cordicjb/u1/d4/cordic Jb/uVd5lft-91- 4i.rtr峠一峠审-片/* 4=-C.%J 号严峠-r.rt- 4/Cordle tb/uVd6/cprdic_tb/u1 /d7-/cordic_tl3/u1/dB/cordic_tb/u1 fd9/cordic tb/tine 50I -ptordicjfo/ul/seqSWin dows(ll)Qatasheetmax 全面 快速 免费的数据喪査询服务 u

28、 Dataflow windowLets you trace sig nals and n ets through your desig n by show ing related processes. Double-click an item with the left mouse butt on to move it to the cen ter of the Dataflow display.VHDL sig nals or processes in theDataflow win dow:?A sig nal displays in the cen ter of the win dow

29、 with all the processes that drive the sig nal on the left, and all the processes that read the sig nal on the right, or ?a process is displayed with all the sig nals read by the process show n as in puts on the left of the window, and all the signals drive n by the process on the right.Win dows(III

30、)u List windowShows the simulati on values of selected VHDL sig nals, and Verilog n ets011101*01111Il5t曰 w Edit Makers Prop VindGW0001Q0*01111*0*n a *0*0000000J *1*0tdic tb/ul/sr/cordi c_tb/ul /sout-/tordic tJb/co?dic_tbAil/ov-KDQGCDZC KXXZXXXZ :XKXXX：C KTOGCOOD：XXXJDQg：zxxsccw; XKZXXXXJ；0SOO 9000 9

31、000 9 SOO 1000Q lOiOO 10500 11000 11000 11500 11500 12000 1200012E00 13000 L3C0D 13MQ 13500 14000 14000 14500001111L010 001111L010 001111L010 0011ULU10 0011111010 OulllllOlO Q011L11Q10 ooimioia Q (111111010 0011111010 Q01H1I010 OOlllltOlO 0011111010 0011111010 0011111010 G0111U010 0011111010 001111L

32、01D D1111LD1G OOlllltOlO 0011111010 001111101000010011 00010011 00010100 onoicioo 00010100 00010101 00010101 00010101 00010110 0Q01011Q 00010110 00010110 00010111 00010111 00010111 00010111 00011000 00011000 00011000 00011000 00011001 000110013Q010011 00010011 00010100 00010100 00010100 OODIDIOI 300

33、10101 00010101 00010110 30010110 OOOIOLLO 00010110 00010111 00010111 aooiom oociom 00011009 00011000 00011000 jooiio ：io 00011001 aaoiiooiXXKJnOOOiXXXXKXXX jooocDcncXZXXXXXa:口菇:OO&COODO ooooooooOOOOOOQO oooooooo 00010001 0001000100010001D0Q1O0C100010011 ocaiooi：00010011 naniooiiXXXKXXXX 阿匚孟g DOOOOOO

34、O ooooooeD 000000 C-0 DOOOOOOD iimiw 11111110 1111111D 11111110 11111110 11111110 11111110Q00000000000and register variables in tabular format.processFile Edit View Windowr.Win dows(IV)u Process windowDisplays a list of processes that are scheduled to run duri ng the curre nt simulati on cycle. ?In

35、dicates that the process is scheduled to be executed with in the curre nt delta time. ?Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time-out period.?In dicates that the process has executed a VHDL wait stateme nt without a time-out o

36、r a sensitivity list. The process will not restart during the current simulation run.3 sa i爲电焜黑i科伸BOUT - i jic_wector( -.)*OV :I atdlogic25 咄27躬29303132333435?! . l.ijrc.tJL t hRCH .! cordlc ic-function of ign tKtenionfuncLion igrvwct(iiN : atd_logic_vectir, esbits . inttQc)variable Y : 3td Logic vc

37、ctor (EKBTT5- dowitc 巧；Win dows(VI)(atasheetmax 全面 快速 免喪的数据裘査询服务 u Source windowDisplays the HDL source code for the desig n.(atasheetmax全面 快速 免费的数据表查询服务(iatasheetmax 全面 快速 免费的数据表査询服务 Win dows(VII-4)?Add Cursor-add acursor to the cen ter of the waveform pan e?Delete Cursodelete the selected cursor f

38、rom the wi ndow?Find Previous Tran siti on-locate the previous sig nal value cha nge for the selected sig nal?Find Next Tran siti on -locate the n ext sig nal value cha nge for the selected sig nal全面快速免费的数据喪査询眾务Windows(VII- 5)?To format an item!Edit Signal Properties_Signal Indicates the name of the

39、 currently selected signal._LabelAllows you to specify a new label (i n the path name pane) for the selected item._HeightAllows you to specify the height (in pixels) ofthe waveform._Name & Wave ColorLets you override the default color of awaveform n ame or Wave by select ing a new color from the col

40、or palette. Tutoriala?1d 3?w 全面 快速 免疫的数据喪査询服务 Experime ntEn vir onment SetupSett ing the Env. for ModelSim?BS yn opsys and Cade neeWorkstation IP:-elnet 140.113.146.23 140.113.146.33 Comma nd-ep asic_ta/sample/.* .-mkdir exp1-cd exp1-ep asic_ta/asic/exp1/* .An example(1)-StartingStep 1.-? slog in g?

41、d?A|b| eOdC?2?1(%) CU?A a? QJvsim?Ki ModelSimaGUIO?- C1?Gftatasheetmax 全面 快速 免费的数据表査询服务 Main wi ndowAn example(2)-Create a libraryStep 2.Main window - Library-Create a New Library-a new library and a logical mapp ing to it1?3G?GCreate a New Library(atasheetmax 全面 快速 免费的数据表査询服务 An example(4)-Load Des

42、ig nStep 4.Main win dow - File - Load New Desig n 1?X?GLoad Desig nAn example(5)-Simulati on(1)Step 5.Mai n wi ndow - View - Sig nalsSig nal wi ndow - wave - Sig nals in Regi on1?G-?G(latasheetmax 全面 快速 免喪的数据表査询眼务 Sig nals wi ndowBiao|浊匚nr Ah 中nw*星勒E tt X 左茹檢锌Q鐵 M U U kJ r ciiibjiSisAn example (6)-Simulatio n(2)(iatasheetmax 全面 快速 免费的数据表査询服务 Lab