X5045带4Kb SPI EEPROM 的CPU监控器中英文翻译

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1、附 录 英文文献4K X5043/X5045 512 x 8 BitCPU Supervisor with 4K SPI EEPROMDESCRIPTIONThese devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces boar

2、d space requirements, and increases reliability.Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.The Watchdog Timer provides an independen

3、t protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling t

4、he power.The devices low VCC detection circuitry protects the users system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds ar

5、e available, however, Xicors unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.The memory portion of the device is a CMOS Serial EEPROM array with Xicors block lock protection. The array is int

6、ernally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicors proprietary Direct Writecell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.FE

7、ATURES Selectable time out watchdog timer Low VCCdetection and reset assertionFive standard reset threshold voltagesRe-program low VCCreset threshold voltageusing special programming sequence.Reset signal valid to VCC= 1V Long battery life with low power consumption50A max standby current, watchdog

8、on10A max standby current, watchdog off2mA max active current during read 2.7V to 5.5V and 4.5V to 5.5V power supplyversions 4Kbits of EEPROM1M write cycle endurance Save critical data with Block LockmemoryProtect 1/4, 1/2, all or none of EEPROM array Built-in inadvertent write protectionWrite enabl

9、e latchWrite protect pin 3.3MHz clock rate Minimize programming time16-byte page write modeSelf-timed write cycle5ms write cycle time (typical) SPI modes (0,0 & 1,1) Available packages8-lead MSOP, 8-lead SOIC, 8-pin PDIP14-lead TSSOPPIN DESCRIPTIONSSerial Output (SO)SO is a push/pull serial data out

10、put pin. During a readcycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.Serial Input (SI)SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of t

11、he serial clock.Serial Clock (SCK)The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.Chip Select (CS)

12、When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high

13、 to low transition on CS is required prior to the start of any operation.Write Protect (WP)When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally.When WP is held high, all functions, including non volatile writes operate normally. WP going low whil

14、e CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write.Reset (RESET, RESET)X5043/45, RESET/RESET is an active low/HIGH,open drain output which goes active whenever VCC falls below the minimum VCCse

15、nse level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer.PRINCIPLES OF OPE

16、RATIONPower On ResetApplication of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insuf-ficient voltage or prior to stabilization of the oscillator.When VCC excee

17、ds the device VTRIP value for 200ms(nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code.Low Voltage MonitoringDuring operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET s

18、ignal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.Watchdog TimerThe Watchdog Timer circuit monitors the microprocessor ac

19、tivity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Reg

20、ister determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure.VCC Threshold Reset ProcedureThe X5043/X5045 is shipped with a standard VCCthreshold (VTRIP)

21、 voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the ap

22、plication of a high voltage control signal.Setting the VTRIP VoltageThis procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIPis 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current

23、setting, then it is necessary to reset the trip point before setting the new value.To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command,followed by a write of Data 00h to address 01h.CS going

24、 HIGH on the write operation initiates the VTRIP programmingsequence. Bring WP LOW to complete the operation.Note:This operation also writes 00h to array address 01h.Resetting the VTRIP VoltageThis procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4

25、.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value.To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage

26、 VP.Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence.Bring WP LOW to complete the operation.Note:This operation also writes 00h to array address 03h.SPI Serial MemoryThe memory portion of the devic

27、e is a CMOS Serial EEPROM array with Xicors block lock protection. The array is internally organized as x8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicors proprietary Direct Write cell, provid

28、ing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.The device contains an 8-bit instruction register that controls the opera

29、tion of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instructi

30、on byte,an 8-bit address, then data bytes. All instruction,address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first.Clock and Data TimingData input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is

31、 output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation.Write Enable LatchThe device contains a Write Enable Latch. This latch must be SET before a Wr

32、ite Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch . This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status registerwrite cycle. The latch is also reset if WP is brought LOW.

33、When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data.Status RegisterThe Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The St

34、atus Register is formatted as shown in “Status Register”.Status Register: (Default = 30H)The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “

35、1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instr

36、uction sets the WEL bit and the WRDS instruction resets the WEL bit.The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any por

37、tion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programm

38、ed with the WRSR instruction.Read Status RegisterTo read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence . The Status Regis

39、ter may be read at any time, even during a Write Cycle.Write Status RegisterPrior to any attempt to write data into the status register, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. T

40、hen bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored.Read Memory ArrayWhen reading

41、 from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored

42、 in the memory at the selected address is shifted out on the SO line. The data stored in memory at the nextaddress can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the high

43、est address is reached, the address counter rolls over to address $000 allowing the read cycle to be continued indefi-nitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence .Write Memory ArrayPrior to any attempt to write data into the memoryarray, the “W

44、rite Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instru

45、ction contains address bit A8, which selects the upper or lower half of the array. If CS does not go HIGH between WREN and WRITE, the WRITE instruction is ignored.The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue t

46、o write up to 16 bytes of data. The only restriction is that the 16 bytes must reside within the same page. A page address begins with address x xxxx 0000 and ends with xxxxx 1111. If the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first

47、address of the page and overwrite any data that has been previously written.For the write operation (byte or page write) to be completed,CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will n

48、ot be completed .While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.OPERATIONAL NOTESThe device powers-up in the following state: The device is in the

49、low power standby state. A HIGH to LOW transition on CS is required to enteran active state and receive an instruction. SO pin is high impedance. The Write Enable Latch is reset. The Flag Bit is reset. Reset Signal is active for tPURST.Data ProtectionThe following circuitry has been included to prev

50、entinadvertent writes: A WREN instruction must be issued to set the WriteEnable Latch. CS must come HIGH at the proper clock count inorder to start a nonvolatile write cycle. Block Protect bits provide additional level of writeprotection for the memory array. The WP pin LOW blocks nonvolatile write

51、operations.中文翻译X5043 X5045带4Kb SPI EEPROM 的CPU监控器一、概述1.1一般说明：X5043/45把四种常用的功能：上电复位,看门狗定时器、电源电压监控和块锁（）保护的串行EEPROM存储器组成在一个封装内。这种组合降低了系统的成本、减小了电路板空间和增加了可靠性。向器件加电时激活了上电复位电路，它保持有效一段时间。这可是电源和振荡器稳定，然后微处理器再执行代码。看门狗定时器对微处理器提供一个独立的保护机制。当系统故障时，在可选的超时时间(time-out-interval)之后，器件将激活信号，用户可以从三个预置的值中选择一个超时时间。一旦选定，即使在

52、断电后重启电源时也不会改变。器件的低Vcc检测电路，可以保护系统免受低电压影响，当Vcc转换点以下时，系统复位。复位一直持续到Vcc回到正常工作电平并且稳定为止。有5个工业标准转换电压门限可以选用，并且Xicor独特的电路允许对门限编程以满足用户的需要或者对高精度应用的精细调整的需要。X5042/45的存储器部分时具有Xicor块锁保护的COMS 4Kb串行EEPROM。该阵列内部的组织是8。器件具有SPI接口特性，其软件协议允许工作在一个简单的四线总线上。器件利用了Xicor公司专有的Direct晶片，提供最小为1000000次擦写和最少100年的数据保存期。1.2特点：u 可选用的看门狗定

53、时器12u 低Vcc检测并产生复位五种标准的复位门限电压用专用的编号顺序调整低Vcc复位门限电压复位信号有效至Vcc1Vu 低功耗使电池寿命长看门狗工作时，等待电流小于50uA（最大）看门狗停止时，等待电流小于10uA(最大)当读数时工作电流小于2mA（最大）u 4KEEPROM可进行一百万次擦写u 用块锁保护保存重要的数据可保护EEPROM阵列的1、1/4、1/2或全部u 内建偶然性的（inadvertent）写保护写使能锁存写保护引脚u 3.3MHz 时钟率u 减少编程时间16字节的写方式自定时间写周期5ms写周期（电性）u SPI方式（0，0和1，1）u 可供封装8引脚SOIC,8引脚M

54、SOP，8引脚PDIP14引脚TSSO1.3引脚排列及引脚说明：SOSO是一个串行数据推/挽输出端。当读周期时，数据从该脚移出。数据由串行时钟的下降沿同步输出。SISI是串行数据输入端。所有要写入存储器的操作码、字节地址和数据都从该引脚输入。输入信号由串行时钟的上升沿锁存。SCKSCK是串行时钟端。串行时钟控制串行总线数据输入和输出的时序。出现在SI引脚的操作码、地址或数据在输入的上升沿被锁存，而SO引脚上的数据在输入时钟的下降沿之后改变。CS是片选端，当为高时，X5043/45未被选中，SO输出端处于高阻抗状态；除非正在进行内部写操作，器件将处于等待方式。为低即使能X5043/45，将它置于

55、激活方式。必须注意：当上电之后，任何操作开始之前，需要先在上有一次由高至低的跳变。WP写保护端。当为低时，向X5043/45的非易失性写被禁止，但器件其它功能正常。当保持高时，所有功能包括非易失性写操作都正常。在保持为低时变低将中断向X5043/45的一次写入。如果内部写周期已经开始，变低对写操作没有影响。复位输出。是低/高有效的漏极开路输出器，只要Vcc下降至低于最小Vcc检测电平时输出端变为有效。它将保持有效值至Vcc上升到最小Vcc检测电平200ms为止，如果看门狗定时器的使能有而且SDA保持HIGH或LOW的时间长于选定的看门狗定时器时间，则将变为有效在有一下降边将复位看门狗定时器二、

56、工作原理2.1上电复位向X5043/45加电是会激活一个“上电复位电路”，它将使引脚有效。这个信号有几种用途：它避免系统的微处理器在电压不足的情况下工作。它避免微处理器在振荡器稳定前工作。当Vcc超时器件的门限值，经200ms（典型）电路释放，允许系统开始工作。2.2低电压监视在工作时，X5043/45监视Vcc电平，如果电源电压跌落到预置的最小以下时，即确认。信号避免了微处理器工作在电源失效或断开的情况下。信号保持有效值直到电压跌落到低于1V。它也保持有效值直到Vcc返回并超过经200ms时。2.3 看门狗定时器看门狗定时器电路通过监视WDI输入来监视微处理器是否激活。微处理器必须周期性的触

57、发/WDI引脚以避免信号。/WDI引脚必须在看门狗超时时间终止之前受到由高至低信号的触发。在状态寄存器中的两个非易失控制位可以决定看门狗的超时周期。微处理器可以改变这些看门狗控制位。没有位控制器的作用，看门狗定时器的控制位保持不变，即使是当全部电源故障时。2.4 重新设置Vcc门限的步骤X5043/45是出厂时是处于标准的Vcc门限电压。这个标准值在正常和存储时是不会改变的，但是在应用中，当标准的并不恰当时，或者需要更精确的值时，X5043/45的门限是可以调整的，这要用到一个高电压控制信号，其步骤说明如下。2.5 电压的设置该步骤用来设置为更高的电压值。例如，如果当前的是4.4V而新的为4.

58、6V，本步骤将直接使之改变。如果新的设置是低于当前的设置，则在设置新值之前先要复位跳变点。为了设置新的电压，加需要的门限电压至Vcc引脚以及编程电压Vp至引脚。然后送WEN命令，接着向地址01h写入数据00h.操作时变高将启动，的编程方式过程。注意：该操作也向地址01h写入00h.。2.5.1 电压的重新设置该步骤用来设置至一个“原始”电压的电平。例如，如果当前的是4.4V而新的必须是4.0V，则必须被复位。当被复位时，新的将稍小于1.7V，为了设置电压至一个较低的电平，必须使用本步骤。为了复位电压，加至少3V至Vcc引脚并将WP引脚接至编程电压Vp。然后送一个WREN命令，接着向地址03h写

59、入数据00h，写操作时变高将启动的编程过程。将WP置为低电平将完成该操作。注意：该操作也向地址03h,写入00h2.6 SPI串行存储器器件的存储器部份是带有Xicor公司的块锁保护的COMS串行EEPROM阵列。阵列的内部组织是8位。器件具有串行外围接口（SPI）和软件协议的特点，允许在简单的四线总线上工作。器件利用Xicor专有的直接写入晶片，提供最小为1000000次擦写和最少为100年的数据保存期。器件设计成可直接与很多通用微控制器系列的同步SPI接口。器件包括一个控制器工作的8位指令寄存器。指令代码通过SI输入端写入寄存器中，有两种只需要指令字节的写操作。有两种用指令字节来启动数据输

60、入的读操作。剩下的操作需要一个指令字节，一个8位地址，然后数据字节。所有的指令，地址和数据位都由SCK信号输入。所有的指令、地址和数据的传送都是MSB在前。2.7 时钟和数据时序在变低以后，在SI线上的输入数据在SCK的第一个上升沿时锁存。在SO线上的数据由SCK的下降沿输出。允许用户停止时钟，然后再启动它以便在它停止的地方恢复操作。在整个工作期间必须为低。2.8 写使能锁存器件有一个写使能锁存（Write Enable Latch）功能。在一次写操作开始以前这个锁存必须被设置。WREN指令将设置该锁存而WRDI指令将复位该锁存该锁存在一次上电和一次有效的字节、页或状态寄存器的写操作完成后自动

61、地复位。如果被来低该锁存也复位。当发出一个WREN、WRD或RESR命令时，不需要送一个字节的地址或数据。2.9 状态寄存器状态器存器包含四个非易失性控制位和两个易失性状态位。控制位设置看门狗定时器的操作和存储器块锁保护。状态寄存器的格式如下。2.9.1 状态器存器格式WIP（Write-In-Progress）位是易失性只读位，它指明器件是否忙于内部非易失性写操作。WIP位用RDSR指令读出。当置“1”时，非易失性写操作正在进行：当置“0”时，没有写操作。WEL(Write Enable Latch)位指出“写使能”锁存的状态。当WEL1表示锁存被设置；而当WEL0表示锁存已复位。WEL位是

62、易失性只读位。WREN指令设置WEL位；而WRDI指令来编程，允许用户保护EEPROM阵列的1/4、1/2、全部或0任何被块锁保护的存储器部份都只能读出不能写入。它将保持到这些BL位有改变，因而存储器受块锁保护的部份也改变为止。WD0，WD1（Watchdog Timer）位选择看门狗的超时周期。这些非易失性位用WRSR指令编程。2.9.2 读状态寄存器为了读状态寄存器，将拉低选中器件，然后先8位RDSR指令然后用CLK信号触发，状态寄存器的内容将SO线上移出。任何时候都可读状态寄存器，甚至是在写周期时。2.9.3 写状态寄存器在想要写数据到状态寄存器之前，“写使能”锁存WEL必须由WREN指

63、令设置。先将拉低，然后送WREN指令至器件，再拉为高。然后再次拉为低，并送入WRSR指令后跟随8位数据。这8位数据相应于状态寄存器的内容。该操作由变高来结束。如果在WREN和WRSR两指令之间不将拉高，则WRSR指令将被忽略。2.9.4 读存储器阵列当要从EEPROM存储器阵列中读出时，只要拉低选中器件。8位READ指令送到器件，后面跟随8位地址。READ指令的位2选择器件的高半部份或是低半部份。在READ操作码和地址送出后，在选定地址的存储在存储器中的数据即在SO线上移出。在连续地提供时钟的条件下储存在存储器下一个地址处的数据可被连续地读出。在每个数据字节移出后，器件即自动将地址增加至下一个

64、更高的地址。当达到最高的地址时，地址计数器即翻转到地址000H，使读周期无限制地连续下去。读操作由拉高而终止。2.9.5 写存储器阵列在要向存储器阵列写玫任何数据之前，必须用WREN指令设置WEL位。首先将CS拉低，然后向器件输入WREN指令，再将拉高。再次将拉低并输入WRITE指令后面跟随8位地址，后面是要写入的数据。WRITE指令的位3是地址位A8，该位选择阵列的高半部份或是低半部份。如果在WREN和WRITE之间不变为高，则WRITE指令将被忽略。WRITE指令至少需要16个时钟脉冲。在操作期间必须保持为低。主机可以连续写入多至16个字节的数据。唯一的限制是16个字节必须在同一页中。一页地址由XXXXX0000开始，由XXXXX1111结束。如果字节地址达到了页中的最后字节而时钟仍在继续，则计数器将返转至该页的第一个地址并重写前面已写过的数据。为了完成写操作（字节写或页写），在最后一个被写入的数据字节的位0完成后必须被拉高。如果它在任何其它时间被拉高，写操作将不完全。在状态寄存器或存储器阵列写入序列后面将跟随一次非易失性写操作。可以读状态寄存器以检查WIP位，若WIP为高则非易失性写正在进行。2.10 操作说明器件上电时处于以下状态器件