数字频率计的介绍外文翻译

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1、、学位论文英文翻译英文原文：Introduction of digital frequency meterDigital Frequency of communications equipment, audio and video, and other areas of scientific research and production of an indispensable instrument. Programming using Verilog HDL Design and Implementation of the digital frequency, in addition to

2、the plastic part of the measured signal, and digital key for a part of the show, all in an FPGA chip to achieve. The entire system is very lean, flexible and have a modification of the scene.1 And other precision measuring frequency Principle.Frequency measurement methods can be divided into two kin

3、ds: (1) direct measurement method, that is, at a certain time measurement gate measured pulse signal number. (2) indirect measurements, such as the cycle frequency measurement, VF conversion law. Frequency Measurement indirect measurement method applies only to low-frequency signals.Based on the pri

4、nciples of traditional frequency measurement of the frequency of measurement accuracy will be measured with the decline in signal frequency decreases in the more practical limitations, such as the accuracy and frequency of measurement not only has high accuracy, but also in the whole frequency regio

5、n to maintain constant test accuracy. The main method of measurement frequency measurement Preferences gated signal GATE issued by the MCU, GATE time width on the frequency measurement accuracy of less impact, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M Signa

6、ls are not overflow line, in accordance with the theoretical calculation GATE time can be greater than the width Tc 42.94 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, generally in the range of between 0.1 s choice, that is, high-fre

7、quency, shorter gate;, low gate longer. This time gate width Tc based on the size of the measured frequency automatically adjust frequency measurement in order to achieve the automatic conversion range, and expanded the range of frequency measurement; realization of the entire scope of measurement a

8、ccuracy, reduce the low-frequency measurement error. The design of the main methods of measuring the frequency measurement and control block diagram as shown in Figure 1. Figure 1 Preferences gated signal GA TE issued by the MCU, GA TE time width of less frequency measurement accuracy, in the larger

9、 context of choice, as long as the FPGA in 32 of 100 in the counter b M signal Overflow will do, according to theoretical calculations GA TE time width T c can be greater than 42194 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, gener

10、ally 10 to 011 s in the inter-choice, that is, high - band, the gate time shorter, low gate longer. This time gate width based on the measured T c automatically adjust the size of frequency measurement frequency range to achieve the automatic conversion, and expanded the range of frequency measureme

11、nt; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.2 Frequency of achievingFrequency Measurement accuracy of such method. Can be simplified as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the

12、 CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counter in the CEN input as enable end, used to control the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flip-fl

13、op input, launched at the same time with two counts of juice; Similarly, when preferences for low gate signal (the end of Preferences time), the rising edge of the measured signals through D Trigger output end of the counter to stop counting.3And the median frequency of relevant indicatorsMedian: At

14、 the same time the figures show that up to the median. The usual eight-count frequency of only several hundred yuan can buy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high. Overflow of:-the ability to promote itself to overflow the equivalent of the

15、 total. Some of the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the purpose of the median. Here is the estimated value of individual indicators. Speed: namely, the number of per second. With the high number of m

16、easurement particularly slow but also lose its significance. Counting of the usual eight frequency measurement 10 MHz signals, one second gate will be 10000000 Hz, which is actually seven (equivalent to the median number of common admission after the value), to obtain eight needed 10 seconds gate ;

17、to obtain nine needed 100 seconds gate, followed by analogy, shows that even the permission of 11 need 10,000 second measurement time. But in any case, or seven per second. Therefore, to fast must be a few high speed. Distinction: it is like a minimum voltage meter can tell how much voltage indicato

18、rs are similar, the smaller the better, unit ps (picoseconds). 1000ps = 1ns. Suppose you use the frequency of 1 ns to differentiate between an e-12 error, we need a ns/1e-12 = 1000 seconds. Also assume that you have a frequency resolution of 100 ps, the measurement time can be shortened by 10 times

19、for 100 seconds, or can be in the same 1000 second measured under an e-14 Error.4 Time and Frequency MeasurementCompared to traditional methods of circuit design, EDA technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilo

20、g HDL description of a multi-level system hardware functions, and support top-down design features. Designers can not understand the hardware structure. Start from the system design, on the top floor of a system block diagram of the structure and design, in a diagram with Ver-ilog HDL acts on the ci

21、rcuit description and simulation and error correction, and then the system level verification, and finally use logic synthesis optimization tool to create specific gate-level logic circuit netlist, download to the specific FPGA device to in order to achieve FPGA design. Time and frequency measuremen

22、t is an important area of electronic measurement. Frequency and time measurement has been receiving increasing attention, length, voltage, and other parameters can be transformed into a frequency measurement and related technologies to determine. Based on the more traditional method of synchronizati

23、on cycle, and has proposed a multi-cycle synchronization and quantitative method of measuring delay frequency method. The most simple method of measuring the frequency of direct frequency measurement method. Direct Frequency Measurement is scheduled to enter the gate signal pulse, the adoption of th

24、e necessary counting circuit, the number of pulses are filled to calculate the frequency or analyte signal cycle. In the direct frequency measurement on the basis of the development of multi-cycle synchronous measurement method, in the current frequency monitoring system to be more widely used. Mult

25、i-cycle synchronization frequency measurement technology actual gate time is not fixed value, but the measured signals in the whole cycle times, and the measured signal synchronization, thereby removing the measured signal count on when the word 1 error, measurement accuracy greatly improved, and re

26、ached in the entire spectrum of measurement, such as precision measurement.In the time-frequency measurement method, the multi-cycle synchronization is a high precision, but still unresolved a word error, mainly because of the actual gate edge and standard frequency synchronization is not filling pu

27、lse edge Tx=N0T0-t2+t1, if accurately measured short interval t1 and t2, will be able to accurately measure time intervals Tx, eliminating a word counting error, so as to further enhance accuracy. To measure a short time interval t1 and t2, commonly used analog interpolation method with the cursor o

28、r more combined cycle synchronization, although accuracy is greatly improved, but eventually failed to resolve a word error this fundamental issue, but these methods equipment complex and not conducive to the promotion. To obtain high precision, fast response time, simple structure and the frequency

29、 and time measurement method is relatively difficult. Judging from the structure as simple as possible at the same time take into account the point of view of accuracy, multi-cycle synchronization and delay based on the quantitative methods in a short period of time interval measurement, achieved wi

30、thin the scope of broadband, such as high-resolution measurement accuracy. Quantified by measuring short time intervals Delay Photoelectric signal can be in a certain stability in the medium of rapid spread, and in different media have different delay. By signals generated by the delay to quantify,

31、and gave a short period of time interval measurement. The basic principle is that delay serial, parallel count, and different from the traditional counter serial number, that is, to signal through a series of delay unit, the delay unit on the delay stability, under the control of the computer Delay

32、on the state of high-speed acquisition and data processing, for a short period of time to achieve accurate measurement interval.Delay quantitative thinking depend on the realization of the delay stability delay unit, the unit depends on the resolution of the delay time delay element. Delay device as

33、 a unit can be passive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate delay time longer. Taking into account delays can be predictive ability final choice of the CPLD devices, the realization of the shor

34、t time interval measurement. Will be the beginning of a short time interval signal sent delay in the transmission chain, when the advent of the end of signal, this signal delay in the delay in the chain latch state, read through the CPU, the judge signal a delay unit on the few short-term time inter

35、val can be the size of the unit decided to delay resolution of the unit delay time. Generally speaking, in order to measure both short interval, the use of two modules delay and latches, but in reality, given the time software gate large enough to allow completion from the number of CPU operation, w

36、hich can be measured in the time interval taken before the end of a short period of time at t1 corresponding delay the number of units through the control signals must be used only a delay and latches units, it saves CPLD internal resources. Synchronization and multi-cycle latency to quantify the me

37、thod of combining The formula is: T=n0t0+n1t1-n2t1On, n0 for the filling pulse of value; t0 for filling pulse cycle, that is 100 ns; n1 for a short period of time at t1 corresponding delay the number of modules; n2 for a short period of time at t2 corresponding delay unit Number; t1 quantify delay d

38、evices for the delay delay unit volume (4.3 ns). In this way, using multi-cycle synchronization and realized the gate and measured signal synchronization; Delay of using quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gat

39、e, it raised frequency measurement accuracy. The frequency synthesizer output frequency signal can only be transferred to the minimum 10 Hz, XDU-17 as a standard of measurement can be calculated prototype frequency measurement accuracy. For example, the measured signal is measured at 15.000010 MHz M

40、Hz signal to 5.00001002, from the calculation can be seen above, the resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysis to illustrate this point.It has been anal yzed,multi-cycle synchronization frequency measurement, the measurement unce

41、rtainty: When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of 110-7/s. When the measurement and quantification of delay circuit with short intervals combined, the uncertainty of measurement can be derived from the following. In the use of cycle synchronization, multi-analyte Tx

42、 for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+t1-t2 Delay circuit and quantitative combined: Tx= NT0+(N1-N2)tdTx Here, Tx not for the accuracy of the measurement. On the decline of the share: Tx2td From the details of the measuring accuracy of this method depends on

43、 the td, and its direct impact on the stability and size of the uncertainty of measurement. Therefore, the application of methods, counters can be achieved within the entire frequency range, such as the accuracy of measurement, and measurement accuracy is significantly improved, measuring improvemen

44、t in resolution to 4.3 ns, and the elimination of the word a theoretical error, the accuracy is increased by 20 times. CONCLUSION This paper presents a new method of measuring frequency. Based on the frequency of this method of digital integrated circuit in a CPLD, greatly reduced the volume of the

45、entire apparatus, improved reliability, and a high-resolution measurements.5 Frequency of VHDL DesignALTERA use of the FPGA chip EPF10K10 companies, the use of VHDL programming language design accuracy of frequency, given the core course, ISPEXPER simulation, design verification is successful, to ac

46、hieve the desired results. Compared to the traditional frequency, the frequency of FPGA simplify the circuit board design, increased system design and the realization of reliability, frequency measurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital log

47、ic design the new trendThis design uses the AL TERA EPF10K10 FPGA chip, the chip pin the delay of 5 ns, frequency of 200 MHz, the standardization of application VHDL hardware description language has a very rich data types, the structure of the model is hierarchical, The use of these rich data types

48、 and levels of the structure model of a complex digital system logic design and computer simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the digital logic can be realized, then can be downloaded to programmable logic de

49、vices, to complete design tasks. -from Vin Skahill.VHDL for Programmable Logic page76-88VHDL Design Flow Its useful to understand the overall VHDL design environment belbre jumping inlo the language itself. Thew aw several steps in a VHDL- based design process, often called the deign flow. These ste

50、ps are applicable to any HDL- based design process and are outlined in Figure pilationHierchay/Block diagramSimulation/verificationcodingfront-endsteps (painful,but no uncommon)TimingverificationFitting/Place+routesynthesis (very painful!)back-endstepsP.1 Steps in a VHDL or other HDL-based design fl

51、ow The so-called flont end begins with figuring out the basic approach and building blocks at the block-diagram level. Large logic design, like software programs, are usually hierarchical, and VHDL gives you a good famework for defining modules and their interfaces and filling in the details later.

52、The next step is the actual writing of VHDL code for modules, their interfaces, and their internal details. Since VHDL is a text-based language, in principle you can use any text editor for this part of the job. However, most design environments include a specialized VHDL text editor that makes the

53、job a little easier; Such editors include features like automatic highlighting of VHDL keywords, automatic indenting, built-in templates for frequently used plogram structures, and built-in syntax checking and one-click access to the compiler.Once youve written some code, you will want to compile it

54、, of course. A VHDL compiler analyzes your code for syntax errors and also checks it for compatibility with other modules on which it relies. It also creates the inlternal information that is needed for a simulator to process your design later. As in other programming endeavors, you probably shouldn

55、t wait until the very end of coding to compile all of your code. Doing a piece at a time can prevent you from proliferating syntax errors,inconsistent names, and so on, and can certainly give you much-needed sense of progress when the project end is far from sight! Perhaps the most satisfying step c

56、ome next-simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its kind you might do as homework in a digital-design class, you would probably generate inputs and observe outputs manually. But for larger projects, VHDL gives you tile ability to create test

57、benches that automatically apply inputs and compare them with expected outputs. Actually, simulation is just one piece of a larger step called verification Sure,it is satisfying to watch your simulated circuit produce simulated outputs, but the purpose of simulation is larger -it is to verify that t

58、le circuit works as desired. In a typical large project, a substantial amount of effort is expended both during and after the coding stage to define test cases that exercise the circuit over a wide range of logical operating conditions. Finding design bugs at this stage has a high value: if bugs are

59、 found later, all of the so-called back-end steps must typically be repeated. Note that there are at least two dimensions to verification. In functional verification, we study the circuits logical operation independent of timing considerations; gate delays and other timing parameters are considered

60、to be zero. In timing verification, we study the circuits operation including estimated sequential devices like flip-flops are met. It is customary to perform thorough functional verification before starting the back-end steps. However, our ability to do timing verification at this stage is often li

61、mited, since timing may be heavily dependent on the results of synthesis and fitting .We may do preliminary timing verification to gain some comfort with the overall design approach, but detailed timing verification must wait until the end. After verification, we are ready to move into the back-end

62、stage The nature of and tools for this stage vary somewhat, depending on the target technology for the design, but there are three basic steps. The first is synthesis, converting the VHDL description into a set of primitives or components that call be assembled in the target technology. For example,

63、 with PLD or CPLD, the synthesis tool may generate two-level sum-of-products equations .With ASIC, it may generate a Iist of gates and a netlist that specifies how they should be interconnected. The designer may help the synthesis tool by specifying certain technology-specific constraints, such as t

64、he maximum number of logic levels or the strength of logic buffers to use. In the fitting step, a fitting tool or fitter maps the synthesized primitives or components onto available AND-OR elements For an ASIC. it may mean laying down individual gates in a pattern and finding ways to connect them wi

65、thin the physical constraints of the ASIC die: this is called the place-and-route process. The designer can usually specify additional constraints at this stage, such as the placement of modules with a chip or the pin assignments of extrnal input and outputpins. The final” step is timing verification of the fitted circuit I