模拟电子和数字电子英文翻译

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1、英文翻译Analog and Digital Ideal Operational Amplifiers and Practical LimitationsIn order to discuss the ideal parameters of operational amplifiers, we must first define the terms, and then go on to describe what we regard as the ideal values for those terms. At first sight, the specification sheet for

2、an operational amplifier seems to list a large number of values, some in strange units, some interrelated, and often confusing to those unfamiliar with the subject. The approach to such a situation is to be methodical, and take the necessary time to read and understand each definition in the order t

3、hat it is listed. Without a real appreciation of what each means, the designer is doomed to failure. The objective is to be able to design a circuit from the basis of the published data, and know that it will function as predicted when the prototype is constructed.1 It is all too easy with linear ci

4、rcuits, which appear relatively simple when compared with todays complex logic arrangements, to ignore detailed performance parameters which can drastically reduce the expected performance.Let us take a very simple but striking example. Consider a requirement for an amplifier having a voltage gain o

5、f 10 at 50kHz driving into a 10 kW load. A common low-cost, internally frequency-compensated op amp is chosen; it has the required bandwidth at a closed-loop gain of 10, and it would seem to meet the bill. The device is connected, and it is found to have the correct gain. But it will only produce a

6、few volts output swing when the data clearly shows that the output should be capable of driving to within two or three volts of the supply rails. The designer has forgotten that the maximum output voltage swing is severely limited by frequency, and that the maximum low-frequency output swing becomes

7、 limited at about 10kHz. Of course, the information is in fact on the data sheet, but its relevance has not been appreciated. This sort of problem occurs regularly for the inexperienced designer. So the moral is clear: always take the necessary time to write down the full operating requirements befo

8、re attempting a design. Attention to the detail of the performance specification will always be beneficial. It is suggested the following list of performance details be considered:1.Closed loop gain accuracy, stability with temperature, time and supply voltage2.Power supply requirements, source and

9、load impedances, power dissipation3.Input error voltages and bias currents. Input and output resistance, drift with time and temperature4.Frequency response, phase shift, output swing, transient response, slew rate, frequency stability, capacitive load driving, overload recovery5.Linearity, distorti

10、on and noise6.Input, output or supply protection required. Input voltage range, common-mode rejection7.External offset trimming requirementNot all of these terms will be relevant, but it is useful to remember that it is better to consider them initially rather than to be forced into retrospective mo

11、difications.All parameters are subject to wide variationsNever forget this fact. How many times has a circuit been designed using typical values, only to find that the circuit does not work because the device used is not typical? The above statement thus poses a tricky question: when should typical

12、values and when should worst-case values be used in the design? This is where the judgment of the experienced designer must be brought to bear. Clearly, if certain performance requirements are mandatory, then worst-case values must be used. In many cases, however, the desirability of a certain defin

13、ed performance will be a compromise between ease of implementation, degree of importance, and economic considerations.Do not over-specify or over-designIn the end, we are all controlled by cost, and it is really pointless taking a sledgehammer to crack a nut, Simplicity is of the essence since the l

14、ow parts count implementation is invariably cheaper and more reliable.As an example of this judgment about worst-case design, consider a low-gain DC transducer amplifier required to amplify 10 mV from a voltage source to produce an output of .l V with an accuracy of 1% over a temperature range of 07

15、0C. Notice that the specification calls for an accuracy of 1%. This implies that the output should be 1 V 10 mV from 0 70C. The first step is, of course, to consider our list above, and decide which of the many parameters are relevant. Two of the most important to this (very limited) specification a

16、re offset voltage drift and gain stability with temperature. We will assume that all initial errors are negligible (rarely the case in practice). The experienced designer would know that most op amps have a very large open-loop gain, usually very much greater than 10000. A closed-loop gain change of

17、 1% implies that the loop gain (as explained later) should change by less than 100% for a closed-loop gain of 100. This is clearly so easily fulfilled that the designer knows immediately that he can use typical open-loop gain values in his calculations. However, offset voltage drift is another matte

18、r. Many op amp specifications include only typical values for offset voltage drift; this may well be in the order of 5 mV/C, with an unquoted maximum for any device of 30 mV/C. If by chance we use a device which has this worst-case drift, then the amplifier error could be 3070=2100 mV=2.1 mV over te

19、mperature, which is a significant proportion of our total allowable error from all sources. Here is a case, then, where one can be confident that the typical value of open-loop gain can be used, but where the maximum value of drift may well cause significant errors. This sort of judgment is essentia

20、l in careful design, and great care is required in interpreting manufacturers data. This consideration must be extended to all the details listed above apart from the fact that worst-case values are often not quoted. It is often found that values given are not 100% tested. Statistical testing is emp

21、loyed which, for example, guarantees that 90% of all devices fall within the range specified. It could be very inconvenient for the user who relies on the specified performance and then finds that he has several of the other 10% actually plugged into his circuit.Data Registers and CountersData regis

22、terThe simplest type of register is a data register, which is used for the temporary storage of a “word” of data. In its simplest form, it consists of a set of N D flip-flops, all sharing a common clock. All of the digits in the N bit data word are connected to the data register by an N-line “data b

23、us”. Figure 1.1 shows a 4 bit data register, implemented with four D flip-flops. The data register is said to be a synchronous device, because all the flip-flops change state at the same time.Shift registers Another common form of register used in computers and in many other types of logic circuits

24、is a shift register. It is simply a set of flip-flops (usually D latches or RS flip-flops) connected together so that the output of one becomes the input of the next, and so on in series. It is called a shift register because the data is shifted through the register by one bit position on each clock

25、 pulse. Figure 1.2 shows a 4 bit shift register, implemented with D flip-flops.On the leading edge of the first clock pulse, the signal on the DATA input is latched in the first flip-flop. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-f

26、lop, and the signal which is present at the DATA input is stored in the first flip-flop, etc. Because the data is entered one bit at a time, this called a serial-in shift register. Since there is only one output, and data leaves the shift register one bit at a time, then it is also a serial out shif

27、t register. (Shift registers are named by their method of input and output; either serial or parallel.) Parallel input can be provided through the use of the preset and clear inputs to the flip-flop. The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asyn

28、chronous (independent of the clock pulse) depending on the design of the shift register. Parallel output can be obtained from the outputs of each flip-flop as shown in Figure 1.3.Communication between a computer and a peripheral device is usually done serially, while computation in the computer itse

29、lf is usually performed with parallel logic circuitry. A shift register can be used to convert information from serial form to parallel form, and vice versa. Many different kinds of shift registers are available, depending upon the degree of sophistication required. Counters weighted coding of binar

30、y numbersIn a sense, a shift register can be considered a counter based on the unary number system. Unfortunately, a unary counter would require a flip-flop for each number in the counting range. A binary weighted counter, however, requires only flip-flops to count to N. A simple binary weighted cou

31、nter can be made using T flip-flops. The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for a binary counter, the “power of two” it corresponds t

32、o. A 3-bit (modulo 8) binary counter could be configured with T flip-flops as shown in Figure 1.4. A timing diagram corresponding to this circuit is shown in Figure 1.5.Note that a set of lights attached to O0, O1, O2 would display the numbers of full clock pulses which had been completed, in binary

33、 (modulo 8), from the first pulse. As many T flip-flops as required could be combined to make a counter with a large number of digits. Note that in this counter, each flip-flops changes state on the falling edge of the pulse from the previous flip-flop. Therefore there will be a slight time delay, d

34、ue to the propagation delay of the flip-flops between the time one flip-flop changes state and the time the next one changes state, i.e., the change of state ripples through the counter, and these counters are therefore called ripple counters. As in the case of a ripple carry adder, the propagation

35、delay can become significant for large counters. It is possible to make, or buy in a single chip, counters which will count up, count down, and which can be preset to any desired number. Counters can also be constructed which count in BCD and base 12 or any other number base. A count down counter ca

36、n be made by connecting the output to the clock input in the previous counter. By the use of preset and clear inputs, and by gating the output of each T flip- flop with another logic level using AND gates (say logic 0 for counting down, logic 1 for counting up), then a presetable up-down binary coun

37、ter can be constructed. Figure 1.6 shows an up-down counter, without preset or clear.Synchronous countersThe counters shown previously have been “asynchronous counters”; so called because the flip-flops do not all change state at the same time, but change as a result of a previous output. The output

38、 of one flip-flop is the input to the next; the state changes consequently “ripple through” the flip-flops, requiring a time proportional to the length of the counter. It is possible to design synchronous counters, using JK flip-flops, where all flip-flops change state at the same time; i.e., the cl

39、ock pulse is presented to each JK flip-flop at the same time. This can be easily done by nothing that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1. A count down timer can be made by connecting the output to t

40、he J and K, through the AND gates. Preset and clear could also be provided, and the counter could be made “programmable” as in the previous case. The timing diagram is similar to that shown for the asynchronous (ripple) counters, except that the ripple time is now zero; all counters clock at the sam

41、e time. It is common for synchronous counters to trigger on the positive edge of the clock, rather than the trailing edge. Nature of Phase LockThe phase detector compares the phase of a periodic input signal against the phase of the VCO. Output of PD is a measure of the phase difference between its

42、two inputs. The difference voltage is then filtered by the loop filter and applied to the VCO. Control voltage on the VCO changes the frequency in a direction that reduces the phase difference between the input signal and the local oscillator.When the loop is locked, the control voltage is such that

43、 the frequency of the VCO is exactly equal to the average frequency of the input signal. For each cycle of input there is one, and only one, cycle of oscillator output. One obvious application of phase lock is in automatic frequency control (AFC). Perfect frequency control can be achieved by this me

44、thod, whereas conventional AFC techniques necessarily entail some frequency error.To maintain the control voltage needed for lock it is generally necessary to have a nonzero output from the phase detector. Consequently, the loop operates with some phase error present. As a practical matter, however,

45、 this error tends to be small in a well-designed loop.A slightly different explanation may provide a better understanding of loop operation. Let us suppose that the incoming signal carries information in its phase or frequency; this signal is inevitably corrupted by additive noise. The task of a pha

46、se lock receiver is to reproduce the original signal while removing as much of the noise as possible.To reproduce the signal the receiver makes use of a local oscillator whose frequency is very close to that expected in the signal. Local oscillator and incoming signal waveforms are compared with one

47、 another by a phase detector whose error output indicates instantaneous phase difference. To suppress noise the error is averaged over some length of time, and the average is used to establish frequency of the oscillator.If the original signal is well behaved (stable in frequency), the local oscilla

48、tor will need very little information to be able to track, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large. The input to the loop is a noisy signal, whereas the output of the VCO is a cleaned-up version of the input. It

49、is reasonable, therefore, to consider the loop as a kind of filter that passes signals and rejects noise.Two important characteristics of the filter are that the bandwidth can be very small and that the filter automatically tracks the signal frequency. These features, automatic tracking and narrow b

50、andwidth, account for the major uses of phase lock receivers. Narrow bandwidth is capable of rejecting large amounts of noise; it is not at all unusual for a PLL to recover a signal deeply embedded in noise.History and applicationAn early description of phase lock was published by de Bellescize in 1

51、932 and treated the synchronous reception of radio signals. Superheterodyne receivers had come into use during the 1920s, but there was a continual search for a simpler technique; one approach investigated was the synchronous, or homodyne, receiver. In essence, this receiver consists of nothing but

52、a local oscillator, a mixer, and an audio amplifier. To operate, the oscillator must be adjusted to exactly the same frequency as the carrier of the incoming signal, which is then converted to an intermediate frequency of exactly 0Hz. Output of the mixer contains demodulated information that is carr

53、ied as sidebands by the signal. Interference will not be synchronous with the local oscillator, and therefore mixer output caused by an interfering signal is a beat-note that can be suppressed by audio filtering.Correct tuning of the local oscillator is essential to synchronous reception; any freque

54、ncy error whatsoever will hopelessly garble the information. Furthermore, phase of the local oscillator must agree, within a fairly small fraction of a cycle, with the received carrier phase. In other words, the local oscillator must be phase locked to the incoming signal. For various reasons the si

55、mple synchronous receiver has never been used extensively. Present-day phase lock receivers almost invariably use the superheterodyne principle and tend to be highly complex. One of their most important applications is in the reception of the very weak signals from distant spacecraft. The first wide

56、spread use of phase lock was in the synchronization of horizontal and vertical scan in television receivers. The start of each line and the start of each interlaced half-frame of a television picture are signaled by a pulse transmitted with the video information. As a very crude approach to reconstr

57、ucting a scan raster on the TV tube, these pulses can be stripped off and individually utilized to trigger a pair of single sweep generators.A slightly more sophisticated approach uses a pair of free-running relaxation oscillators to drive the sweep generators. In this way sweep is present even if s

58、ynchronization is absent.Free-running frequencies of the oscillators are set slightly below the horizontal and vertical pulse rates, and the stripped pulses are used to trigger the oscillators prematurely and thus to synchronize them to the line and half-frame rates (half-frame because United States

59、 television interlaces the lines on alternate vertical scans).In the absence of noise this scheme can provide good synchronization and is entirely adequate. Unfortunately, noise is rarely absent, and any triggering circuit is particularly susceptible to it. As an extreme, triggered scan will complet

60、ely fail at a signal-to-noise ratio that still provides a recognizable, though inferior, picture.Under less extreme conditions noise causes starting-time jitter and occasional misfiring far out of phase. Horizontal jitter reduces horizontal resolution and causes vertical lines to have a ragged appea

61、rance. Severe horizontal misfiring usually causes a narrow horizontal black streak to appear.Vertical jitter causes an apparent vertical movement of the picture. Also, the interlaced lines of successive half-frames would so move with respect to one another that further picture degradation would resu

62、lt.Noise fluctuation can be vastly reduced by phase locking the two oscillators to the stripped sync pulses. Instead of triggering on each pulse a phase-lock technique examines the relative phase between each oscillator and many of its sync pulses and adjusts oscillator frequency so that the average

63、 phase discrepancy is small.Because it looks at many pulses, a phase lock synchronizer is not confused by occasional large noise pulses that disrupt a triggered synchronizer. The flywheel synchronizers in present day TV receivers are really phase-locked loops. The name “flywheel” is used because the

64、 circuit is able to coast through periods of increased noise or weak signal. Substantial improvement in synchronizing performance is obtained by phase-lock.In a color television receiver, the color burst is synchronized by a phase-lock loop.Space flight requirements inspired intensive application of

65、 phase lock methods. Space use of phase lock began with the launching of the first American artificial satellites. These vehicles carried low-power (10 mW) CW transmitters; received signals were correspondingly weak. Because of Doppler shift and drift of the transmitting oscillator, there was consid

66、erable uncertainty about the exact frequency of the received signal. At the 108MHz frequency originally used, the Doppler shift could range over a 3kHz interval.With an ordinary, fixed-tuned receiver, bandwidth would therefore have to be at least 6kHz, if not more. However, the signal itself occupies a very narrow spectrum and