本科毕业论文---基于建模的方法评价评估实时嵌入式控制系统的性能外文翻译

《本科毕业论文---基于建模的方法评价评估实时嵌入式控制系统的性能外文翻译》由会员分享，可在线阅读，更多相关《本科毕业论文---基于建模的方法评价评估实时嵌入式控制系统的性能外文翻译（78页珍藏版）》请在装配图网上搜索。

1、英文资料翻译A modeling-based methodology for evaluating the performance of a real-time embedded control systemKlemen Perko, Remy Kocik, Redha Hamouche, Andrej TrostABSTRACTThis paper presents a modelling-based methodology for embedded control system (ECS) design. Here, instead of developing a new methodol

2、ogy for ECS design, we propose to upgrade an existing one by bridging it with a methodology used in other areas of embedded systems design. We created a transformation bridge between the control-scheduling and the hardware/software (HW/SW) co-design tools. By defining this bridge, we allow for an au

3、tomatic model transformation. As a result, we obtain more accurate timing-behaviour simulations, considering not only the real-time software, but also the hardware architectures impact on the control performance. We show an example with different model-evaluation results compared to real implementat

4、ion measurements, which clearly demonstrates the benefits of our approach. 2011 Elsevier B.V. All rights reservedKEY WORDS: Modeling, Model transformations, Embedded control systems design, Real-time systems1. IntroductionEmbedded control systems (ECSs) are ubiquitous nowadays. They are used in a br

5、oad spectrum of applications, from simple temperature control in household appliances to complex and safetycritical automotive brake systems or aircraft flight control systems. Different applications have different demands with regards to the real-time execution, control performance, energy consumpt

6、ion, price, etc., of the ECS being used. Modern technologies for hardware (HW) and software (SW) design provide a variety of possibilities for designing ECSs (e.g., distributed and networked HW, multi-processor systems, a variety of SW control algorithms and real-time operating systems (RTOSs), etc.

7、) 1. It is commonly acknowledged that the designing and verifying of reliable and efficient ECSs for a particular application are challenging tasks.1.1. Traditional control-system designThe aim of designing an ECS is to build a computing system that is able to control the behavior of a physical syst

8、em, e.g., a plant. Such a plant is made up of interconnected mechanical, electrical and/or chemical elements. A typical ECS consists of electronic sensors for data acquisition from the plant, a computing system for processing the control algorithm, and electronic actuators to drive the plant.The ECS

9、 design process involves different actors and areas of expertise (control theory, signal processing, real-time SW and HW engineers). Each of these engineers is familiar with their own modeling languages, models, design tools, etc. This heterogeneity introduces cuts in the design process. Model trans

10、formations are needed between each design step; however, they are often carried out manually and, as a result, are prone to mistakes and subject to interpretation, which of course depends on the skill of the designer. The traditional form of ECS design is performed in two separated domains the contr

11、ol SW domain and the HW domain using specific design tools and their respective system models. In the first domain, control engineers define the control laws and the SW engineers write the code that executes the operations required by the control laws. A so-called control-scheduling co-design is per

12、formed. Decisions made in the real-time (RT) software design affect the control design, and vice versa. For instance, different SW scheduling policies have different impacts on the latency distributions in the control loops and, consequently, on their performance. Also, the control-loop performance

13、directly affects (by constraining) the SW execution parameters (i.e., sampling periods, task-execution jitter, etc.).In the second domain the HW engineers design an HWplatform that will execute the control SW. The connections of all the sensors and actuators to the platform are made via the availabl

14、e communication channels. However, because the HW platform is designed separately, control engineers cannot estimate its impact on the control-loop performance. For instance, the data from sensors and to actuators can pass through one or more communication channels. A HW engineer can, in general, ch

15、oose from among a variety of communication protocols, and each type introduces different latencies and jitter, which therefore affects the SW execution. The control engineer cannot, however, evaluate the effect of these latencies before the system is actually implemented. Hence, the desired performa

16、nce of the system may not be achieved, and it is necessary to change and tune the control laws (calibration phase) in order to compensate for the impact of these communication and execution delays. The fact that the calibration has to be performed on an actual plant can be very expensive and time-co

17、nsuming, especially when the desired performance cannot be achieved using the current HWplatform and a redesign is required. Another shortcoming of traditional ECS design is the inability of control and SW engineers to exploit some of the advantages offered by modern HW technologies. For instance, c

18、ontrol loops running in parallel, instead of the traditional sequential execution, could give better performance. Parallel execution can be achieved with the use of multi-processor or distributed platforms.Modern ECS design techniques rely heavily on system modeling, which provides a means to examin

19、e how various components work together and to estimate the impact of the ECSs implementation on control performance before it is actually implemented. This makes it possible to correct the initial control laws in order to compensate for the implementation impacts early in the design cycle. Another i

20、mportant aspect of modeling is the ability to explore different possible system implementations (design-space exploration). Appropriate modeling can significantly shorten the design cycle of an ECS 2.To overcome the problems introduced by the heterogeneity of design models and tools, different metho

21、dologies and tools were developed 3. These methodologies usually provide a means to create a uniform ECS model, simulate and evaluate its behavior, formally transform it towards an implementation, etc.1.2.Proposed control system designTo improve and accelerate the traditional ECS design we propose t

22、he merging of these separated domains. On the basis of this merging, all the actors in the design process could better collaborate and exchange their data during the design process, they could do a more thorough design-space exploration and the design cycle could be made significantly shorter. Inste

23、ad of developing a new methodology for ECS design, we propose to upgrade the traditional SW-based control-system design approach with efficient modeling and design of the HW platforms. Recently, several methodologies have been developed that concern HW/SW co-design. These methodologies enable the ef

24、ficient design of SW and HW on embedded systems in terms of SW execution speed, HW resources usage, system flexibility, future upgradeability, final design costs, etc. We propose creating a formal bridge between the existing tools for control-scheduling co-design and HW/SW co-design. This bridge mak

25、es possible model transformations and the exchange of simulation results between tools for control-scheduling co-design and HW/SW co-design.The bridge is based on a formal transformation of models between different design tools. Our foundation for the control scheduling co-design methodology is work

26、 presented in 4 and its associated tool, MoDEST, which is presented in 5. For the purpose of HW/SW co-design we have selected the methodology presented in 6 with its associated abstract-system modeling tool, ASyMod, which is presented in 7.With the bridge we are able to obtain more accurate control-

27、performance evaluations considering architectural details and even the possibility to study mixed HW/SW implementations of the control system. Evaluating the impact of implementation in the early design stages reduces the number of design-lifecycle iterations and shortens the time needed for a final

28、 calibration of the control laws.In the next section we present the related methodologies, followed by short descriptions of the MoDEST and ASyMod tools and their metamodels. In Section 3 we describe the formal rules for model transformation and the implementation of the bridge. In Section 4, two ex

29、amples of an embedded controller are presented. By comparing simulation results to measurements on a real implemented system, we show the benefits of our approach. Finally, the paper is concluded in Section 5.1.3.Related methodologies and toolsThe increasing need to optimize ECSs in terms of their c

30、ontrol performance, RT constraints and cost efficiency has led to limited computational resources combined with their efficient exploitation and has, as a consequence, encouraged the emergence of new research areas.Domain-specific tools for control-scheduling co-design have been developed recently.

31、These tools support implementation modeling and analysis in terms of control performance. Several of the tools are based on Matlab, which is traditionally used by control engineers for the design of control laws. The AIDA 8 toolset is a model-based environment for the design and analysis of control

32、systems, used either in stand-alone form or with Matlab. The toolset supports the modeling of control-function execution on distributed HW components containing multi-processors and communications links. The effects of the control algorithms implementation on control performance can be analyzed. Jit

33、terbug 9 is a Matlab-based analysis tool for computing a quadratic performance criterion in linear control systems under various timing conditions. Using Jitterbug, the sensitivity of control systems to delays, jitter and other interferences can be studied. The effects of different SW implementation

34、s on control performance can be analyzed. TrueTime 10 is a simulator in Matlab/Simulink designed for the co-simulation of the distributed controllers task execution on several RT kernels, network transmissions, and continuous plant dynamics. It provides a control performance analysis of distributed

35、RT computer-based control systems, considering the effects of processors and network scheduling, task attributes, their data dependency, etc. TrueTime and Jitterbug can be used together to evaluate the performance of various control loop implementations 11. Recently an ESMol 12 tool chain has been d

36、eveloped. It incorporates a prototype scheduling tool which calculates schedules for time-triggered networks in distributed embedded systems. The ESMoL can be used together with the TrueTime in order to asses platform effects to computed schedule and to control performance.The research activities fo

37、cused on software design for distributed real-time embedded systems lead to development several tools and languages. Timing Definition Language (TDL) is a high-level description language for specifying the explicit timing requirements of a time-triggered application, which may be constructed out of

38、several components. It promotes the idea that the functional and temporal behavior of developed software should be platform independent. This reduces costs of system integration, validation and maintenance. An automatic bus-schedule generation for messages over network topology is presented in 13. A

39、n approach to optimize software component allocation systems on distributed real-time embedded systems is explained in 14. Authors provide bin packing algorithm for deployment and configuration of components in order to meet their required quality-of-service (QoS) properties, such as predictable lat

40、ency/jitter, throughput guarantees, scalability etc. Cheddar tool is designed for software task scheduling simulation and feasibility analysis of systems described with Architecture Analysis & Design Language (AADL). Methods for scheduling analysis and memory requirements analysis of buffers used fo

41、r communication between AADL threads are described in 15.Researchers have defined several HW/SW co-design methodologies in order to leverage system development. Multicomponent architectures allowing RT implementations of complex algorithms at a low cost have been proposed. Several tools have been in

42、troduced for system modeling 16, synthesis 17 and design 1820. Ptolemy II 16 supports a variety of models of computation, for example, a timed multitasking model 21 for a deterministic design of the concurrent RT software. The tool is able to model a fixed-priority scheduling of tasks with constant

43、execution times. SynDEx 20 is a co-design tool for rapid prototyping and optimizing the implementation of distributed RT embedded applications onto multicomponent architectures. It includes automatic mapping and scheduling, supports architecture refinements and the automatic generation of the execut

44、able code.The complexity of the algorithms, reusability and traceability, demand a reduction in the design costs, and the diversity of skills and tools involved in the design process has driven researchers to define a new model-driven methodology. The Model- Driven Engineering (MDE) approach relies

45、on using the concepts of models as an abstract presentation of the system. The model is always constructed with a specific purpose in mind and is not intended to represent the system as a whole. The semantics of the concepts and relations handled in the model has to be precisely specified. The role

46、of the metamodel is to define what the valid models express, e.g., a model is conformable to a metamodel. Metamodels are defined using one of the modeling languages. The approach was first applied in the SW engineering domain 22, but later it has also been increasingly used in the design of embedded

47、 systems 12,14,23,24.In the MDE approach, models evolve with model transformations classified into vertical and horizontal transformations 25. A typical example of the horizontal transformation is model migration, and an example of the vertical transformation is model refinement. Vertical transforma

48、tion steps add more details to the model with respect to the previous step. Each vertical refinement step leads to a more detailed model, while still implying the properties of the abstract model from the first step. The level of abstraction is lowered towards the implementable model. The horizontal

49、 transformation is a transformation where the source and the target models reside at the same abstraction level, but the model can migrate from one tool to another. With horizontal transformations, different bridges between the tools can be established. For vertical and horizontal transformations di

50、fferent approaches and related languages have been developed that provide transformation environments. Acknowledged representatives of model transformation languages are ATL 26, 27 and GReAT 28, 29. Transformation in GReAT relies on graph transformation techniques, while in ATL transformation is bas

51、ed on textual written rules. GReAT is used for model transformations in 14. Detailed overview and comparison of model transformation tools and approaches can be found in 30.Our work is at the crossroads of the above research areas. Using the MDE approach based on metamodelling, we offer a design fra

52、mework that supports model transformations so as to enable links between different tools, such as those mentioned above. Within the tool we provide scheduling simulation as in 15. It provides analysis of software tasks execution time jitter to control performance. A model transformation bridge with

53、HW/SW co-design tool extends this analysis to consider also the impact of hardware architecture components and also enables architectural exploration.2.Model-driven embedded system design2.1.MoDEST toolThe Model-Driven Embedded System Design Tool (MoDEST) tool 5 implements the methodology presented

54、in 31. Its main goal is to unify the ECS design steps into a homogeneous approach, by handling the complexity and the heterogeneity of models, and to improve the models consistency and tractability along the design stage in V-shaped ECS design process as presented in Fig. 1. The MoDEST tool offers a

55、 design environment ranging from control-algorithm modeling to code generation for a mono-processor target. The tool does not replace specialized domain tools, but enables the building of links between them in order to support, in the same framework, the whole embedded-system design process.The MoDE

56、ST tool implements multi-facet design views, where each view is well suited to the job and the problems of each design step. It provides a domain-oriented toolset for building a model, using a specific terminology (control, computer-science or RT), with the corresponding actor (control designer or R

57、T software designer). These domain-oriented languages are based on a SW-component approach, effectively accelerating the design cycle. The component approach increases the reusability of models, despite the rapid technological evolution of embedded platforms. The embedded control system is designed

58、on the basis of three facets: functional, SW specification and implementation. In the functional facet, the user defines the algorithm using a dataflow graph, where the nodes are the functions and the data dependencies are the signals. In the SW specification facet, the user specifies the software c

59、omponents (IComps) that will implement the necessary functions, for composing the complete control algorithm. In the implementation facet, according to the RT constraints and data dependencies, IComps are grouped into sequences executed in periodic tasks. In this facet, the user should also give inf

60、ormation about the HW resources and the SW platform, such as the scheduling policy.The Model-Driven Architecture (MDA) approach is used; this raises the embedded-system design process from a classical code-oriented development to a model-driven development with automatic code generation. The tool re

61、lies on a proposed metamodel able to capture the three facet descriptions by defining a unified terminology and semantics to share the information without having to duplicate it. Thus, it ensures consistency between the models used in each design step by carrying out model transformations and reconc

62、iliation between the facets: each change in the facet description is automatically relayed to another one.The tool provides facilities for scheduling analysis and simulation as well as code generation for multiple targets. It includes an RT behavior-analysis module to check the scheduling feasibilit

63、y (Rate Monotonic (RM), Deadline Monotonic (DM), Earliest Deadline First (EDF), etc.). It is also able to simulate and display, as a chronogram chart, the execution of tasks. The code-generation and profiling module, which generates the source codes for the multiple RT kernels (RTAI 32, DSPBios 33 a

64、nd real-time Java) and captures a real temporal execution trace, has also been implemented. The MoDEST tool also provides a timing-measure module that performs latency, delay and jitter measurements on task execution. This temporal information can be used in hybrid simulations in order to estimate t

65、he loss of control performance.2.1.1Metamodel of the MoDEST implementation facetThe bridge between the MoDEST and ASyMod tools is based on rules defining the transformations between a subset of the MoDEST Metamodel (Implementation Facet part) and the ASyMod Metamodel. Since the goal of the paper is

66、to describe the bridge, we will not present details of the whole MoDEST Metamodel but only of the subset relevant to the implementation facet. For the sake of simplicity, we shall term it the MoDEST Metamodel. A snippet of the metamodel is presented in Fig. 2.To define the metamodel, we use a graph notation. A data-flo