通信工程专业数据采集系统中英文资料外文翻译文献

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1、通信工程专业数据采集系统中英文资料外文翻译文献通信工程专业数据采集系统中英文资料外文翻译文献 通信工程专业数据采集系统中英文资料外文翻译文献 高速数据采集系统的设计 摘要：为满足雷达信号采集的要求，设计了一种基于PCI总线的12 bit100 MS / s的数据采集系统。该系统可实现6 GB数据的实时采集和存储。可编程逻辑器件控制数据收集，存储和传输。使用PCI主模式的PCI数据传输，传输速率达到60M字节/秒，收集到的信号的信噪比可以达到55 dB。 关键词：PCI控制器;可编程器件;抖动。 1.总述 随着通信，雷达等领域的快速发展，所需处理模拟信号的带宽和动态范围也越来越大，DAC采样速度

2、和精度要求越来越高。高速度和高精度的数据收集所需的存储器带宽变得越来越大，因此，如何提高数据存储器带宽已经成为高速数据采集系统设计的瓶颈之一。 雷达系统的数据采集系统时钟采样频率要求是至少100兆赫，对至少10位DAC分通信工程专业数据采集系统中英文资料外文翻译文献 频。而现有的计算机系统满足不了雷达系统的实时传输的要求。但雷达信号的有用信息只占其中一小部分。如图1，因此，只要将有用信息采集和储存，则可实现雷达信号样本实时存储。 图1 根据雷达信号采集和存储的特性，本文设计一个12 bit100 MS / s的数据采集系统。该系统采用了PCI总线连接到计算机，数据采集系统利用板卡大容量信息对有

3、用信息进行实时处理，数据采集由系统外部出发信号控制。 2.数据采集卡框架 整个采集系统分为以下四个部分：模拟信号调制部分，时钟脉冲处理模块，数据缓存模块，数据传输和触发模块。如图2所示。 图2 2.1模拟信号调制 模拟信号的调制包括：模拟信号前放，信号数控增益，单端转差分布。模模拟信号前置运放采用AD9631实现输入信号的阻抗匹配及信号的低通滤波。在一个雷达系统中，从不同的雷达站收集扫描目标的雷达信号振幅是不同的，并且为了提高采集系统的信噪通信工程专业数据采集系统中英文资料外文翻译文献 比，应使ADC的模拟输入信号的幅度接近满幅。所以将一个压控增益运算放大器AD603芯片加到前置运算放大器之后

4、，以调节ADC输入信号的范围。电压控制AD603的增益芯片的模拟带宽在90 MHz时， 增益范围-11 dB一30 dB。由一片8位DAC芯片产生压控芯片的的增益电压，DAC的芯片选择MAX503 MAXIM公司出品，芯片数字输入由FPGA控制和产生。数据采集系统的ADC 是由AD公司12位100兆赫AD9432 的芯片，该模拟信号为45MHz仍然具有65 dB的信噪比。由于该ADC模拟信号为差分输入差，因此,从压控增益芯片AD603输出的模拟信号经过单端转差分芯片AD8138连接到ADC芯片上，从ADC输出的12 bit数字信号直接连接到FPGA芯片上。 2.2 时钟模块 为了增加所述采集系

5、统的灵活性和通用性，该ADC采样时钟芯片可以是从外部时钟，也可以从内部时钟。采样时钟的选择由板卡跳线器决定。外部时钟通过SMA连接器连接到电路板上，外部时钟信号为TTL电平，由于ADC的采样时钟需要PECL电平，因此，外部时钟时钟由PECL电平转换芯片MClOELl6连接到时钟选择模块。 ADC的内部时钟是由该系统的数控时钟模块生产。 时钟模块选择频率合成器是NC SY89429。时钟输出的范围在25兆赫至400兆赫之间，用于PECL输出信号，可直接连接到ADC的采样时钟。该频率合成器的时钟输出可被芯片的11位数字信号控制，可以精确调节输出时钟精度至1兆赫兹。 11数字信号由FPGA控制。在数

6、据采集系统中，特别是在高速数据采集系统，该时钟是一个非常重要的信号，不同时钟抖动相差较大。当采集系统的输入模拟信号带宽较大时，在计算采集系统的信噪比时钟抖动不能被忽略。量化噪声的因素也需要考虑“1，12位的ADC，当输入信号的频率为40 MHz时，信噪比和采样时钟抖动曲线如图3所示，横坐标为对采样时钟抖动，y坐标为采集系统的信噪比。从图3中可以看出，为使ADC的采集系统的信噪比大于50 dB，采样时钟抖动必须控制在10 ps以内，否则，在所造成的外部时钟抖动会降低AD9432的性能。本系统中采用SY89429芯片，输出时钟抖动峰最大值为25 ps，时钟抖动均方根为10 ps左右，满足系统的设计

7、要求。如果要使用外部时钟，必须选择具有低抖动外部时钟源。 通信工程专业数据采集系统中英文资料外文翻译文献 图3 2.3高速数据缓存模块 高速ADC数据存储由A1tera公司生产的Cyclone FPGA芯片控制。如图4的逻辑结构 数据采集系统使用MICRON公司的2片MT48LC4M16A2SDRAM并联作为系统的片上存储器。并联SDRAM内存位宽为32位，16 MB的容量，100 MHz的时钟频率。比的SRAM芯片的SDRAM的芯片具有更高的工作速度，容量更大，为系统提供了设计的灵活性。为了改善的SDRAM的传输带宽，SDRAM控制器突发长度14总线将数据传送到SDRAM控制器，由SDRAM

8、控制器把该数据写入到外部的SDRAM芯片。虽然外部SDRAM芯片的数据总线宽度为32位，但实际使用只有24位，也就是理论上的SDRAM总线传输带宽为300 MB /秒。考虑到SDRAM的刷新和突发传输开销，实际通信工程专业数据采集系统中英文资料外文翻译文献 上可以实现200MB / s，而ADC的采样数据传输带宽为150 MB /秒，因此，这足以满足SDRAM控制器实时采样数据存储。存FIF0的容量为2 KB，宽为24位。由于SDRAM的操作包括SDRAM的刷新，突发读取和写入操作，由于从存储控制模块输出的数据没有被存储在实时的SDRAM中，所以使用存FIFO完成的数据存储速度匹配和数据存储在

9、FPGA芯片中暂存。存储器读控模块负责向SDRAM控制器发起突发写操作，由于SDRAM控制器采用突发传输操作，所以每次控制模块必须向SDRAM存储器发送一块，这需要ADC传输的数据的量必须是16的倍数，也符合实际需求。为了提高WB写入总线的传输性能，存储器读控制模块一次检测到在存FIFO中的数据的存储量大于或等于一个块，启动WB写总线操作。在整个数据采集系统，SDRAM以环形形式存储采样数据，提高了使用的SDRAM的效率，简化了系统的逻辑设计。 2.4数据传输和触发模块 使用AMCC公司的PCI主控器件s5933传输采样数据到计算机的内存中。 S5933是一种特殊的功能非常强大的，灵活运用PC

10、I总线的控制器芯片。它完全符合PCI局部总线规范2.1l，不仅可以做PCI总线从设备，并且可以做PCI总线主设备进行数据传输。 S5933拥有三个接口：PCI总线接口，ADDON总线接口和外部NVRAM参数配置界面。 PCI总线接口和连接到该PCI总线的计算机的插槽相连。计算机与用户端可以通过ADDON总线接口的FIF0通道、PATHTHRU通道进行相互通信。PCI总线通过使用PATH . THRU渠道实现和客户信息的交互。客户端利用FIFO通道把本地存储数据通过计算机的PCI总线传递到计算机内存中。计算机使用S5933的PASS。TRU操作控制FPGA的内部寄存器。当计算机发出的PCI地址落

11、在PASSTHRU定义的某个区中时，s5933通过PTATN向FPGA的PATHTRU控制及译码逻辑发出请求。PATHTRU控制与译码逻辑根据 PTADR信号判断本次操作是PATH-TRU读操作还是写操作，利用PTADR信号获取本次PATHTHRU操作的地址信息(该地址存放在s5933的PATHTRU地址寄存器内部)。FPGA使用PATH - THRU地址信息对应的解码操作，选通内部不同的寄存器： 根据计算机收集到的模拟信号最大数值，通过数控增益DAC寄存器使ADC的模拟信号输入是接近全振幅。 通信工程专业数据采集系统中英文资料外文翻译文献 通过ADC采样时钟寄存器设定ADC采样时钟工作。 设

12、置ADC需要收集数据的总量：数据总量为32位的寄存器，足以满足现有的雷达系统的需要，总数据寄存器必须是16的倍数。 通过模式配置寄存器设置ADC高速数据采集系统的操作模式：设置ADC的外部触发信号触发模式，设置ADC采样信号的软件触发或硬件触发，可以控制ADC采样。 设置触发延迟时间：雷达系统的采样时间触发延时可以通过寄存器进行设置 根据触发模块触发条件，采样的数据量和单次触发采样数量产生触发使能信号，该信号相当于存FIF0写使能信号。 计算机使用S5933的 PCI主模块FIF0通道实现采样数据到计算机内存的自动传输。s5933内部的FIF0通道写操作由FPGA完成，读操作由s5933内部控

13、制器完成。一旦检测到S5933 WRFULL信号是无效的，或PCI主模块写FIF0通道不满时，则从非空传双时钟FIFO读取数据，并写入到S5933的PI主模块的写FIFO的数据通道。 高速缓存块数记录SDRAM控制器里面有多少数据块要发送，在写入数据的一个块中，SDRAM的高速缓存块数上升1，当读取从SDRAM数据的一个块，高速缓存块是减去1。 传双时钟FIFO的写控制由传读控制逻辑完成。传读控制逻辑，传双时钟FIFO的写控制由传读控制逻辑完成。传读控制逻辑只有在采集数据没有传输完毕且传双时钟FIF0非满时，才启动wb读总线操作，从SDRAM缓冲区读取一个数据块并把该数据块写入传双时钟FlF0

14、中。 wishbone总线仲裁模块实现wb写总线与wb读总线的仲裁，其采用固定优先级的方式，wb写总线的优先级比wb读总线的优先级高，保证了采样数据的实时本地存储。 3.软件设计 为了提高数据传输速率，并降低了CPU资源占用，数据采集是通过使用PCI主动控制方式来实现数据到计算机内存的传输。然而由于S5933芯片单次传输数据的最大数量64 MB，所以如果你想连续发送大于64 MB的数据，则需要多次启动主模式数据传输。在数据传输的过程中，CPU不进行过程控制。软件首先执行PCI总线扫描，获得S5933通信工程专业数据采集系统中英文资料外文翻译文献 芯片占用 PCI配置的空间地址，然后向操作系统申

15、请用于收集数据被传递到计算机的存储器的物理空间，并且将该地址映射到s5933PCI主设备的物理空间。然后软件配置S5933芯片内部寄存器，包括DMA传输数据量和PCI总线传输特性等寄存器，并且可以使s5933PCI主控操作。 S5933等待FPGA发送采集数据，如果S5933内置写FIFO芯片的通道不为空，则发起PCI总线操作把数据传递到计算机内存中。软件根据实际雷达需求通过s5933的PASS-TRU操作对FPGA内部相关寄存器进行配置，设置数据采集系统相关参数，并触发使能FPGA数据。雷达信号的数据采集和存储由硬件自动完成，当采样数据到达S5933单次数据传输量时，S5933向计算机申请一

16、个中断。软件在中断处理程序完成取样数据的读取和库存操作，并且对采样的数据进行了相应的处理，例如FFT变换。在计算机进行多次DMA数据传输参数设置期间，数据采集卡的大容量的高速缓存以确保样本数据存储的无损失。 4性能分析与测试 在本文中，数据采集系统的采样频率为25兆赫到100兆赫，可以动态地按1兆Hz步长进行调整。采集系统来支持多个外部触发模式，外部触发方式由可编程逻辑器件动态设计。板卡内置的32 MB内存储器决定了有用信息的采集时间，在采样频率100兆赫时，有用信息获取时间可以达到160 ms. 该采集系统可实时传输的数据量受可编程逻辑器件寄存器的大小的和计算机内存的大小限制，该系统采用了3

17、2位寄存器，能够传输的数据理论总量为2个采样点，即6 GB。 设计的数据采集系统经过测试，PCI传输速度是60 MB / s的，在100兆赫的工作频率下为了实现雷达信息的实时采集，雷达系统的扫描周期与有用信息采集时间之比应该大于2.5。本系统涉及的雷达有用信息采样时间为72s，雷达扫描周期为360 us，因此，在本文中，高速数据采集系统能够满足雷达系统的实时存储和传输的需求。测试表明，该系统信噪比超过55分贝，该雷达系统能够满足需求的性能。 5 .结束语 32通信工程专业数据采集系统中英文资料外文翻译文献 在本文中，根据雷达信号的特性来完成高速数据采集系统的设计。该系统可以完成实时雷达信号的采

18、集和存储，该系统的SNR性能达到了雷达的需求。由于采用可编程逻辑器件，所以该系统能够满足其他场合的需要。 High speed data acquisition system design Abstract: to meet the requirements of radar signal acquisition, design a 12 bit100 Ms/s data collection system based on PCI bus. The system can realize 6 GB of data real-time collection and storage. Progra

19、mmable logic devices to control data collection, storage and transmission. PCI data transmission using PCI main mode, transmission rate reached 60 MB/s, the signal-to-noise ratio of the signal collected at 55 dB (30 MHz analog signals). Key words: the PCI controller; Programmable device; jitter. 1.

20、Summarize With the rapid development of communication, radar, and other fields, to deal with 通信工程专业数据采集系统中英文资料外文翻译文献 analog signal bandwidth and dynamic range is more and more big, the DAC sampling speed and precision demand is higher and higher. High speed and high precision data gathering the requ

21、ired memory bandwidth is becoming more and more big, therefore, how to improve the data memory bandwidth has become one of the bottleneck of high-speed data acquisition system design. Radar system requirements of data acquisition system clock sampling frequency is 100 MHZ, at least for at least 10 b

22、it DAC points frequency. While the existing computer system satisfies the requirement of the real-time transmission of radar system. But radar signal useful information make up only a small part of them. As shown in figure 1, therefore, as long as the collection and storage of useful information can

23、 realize the real-time radar signal samples storage. figure 1 According to the characteristics of radar signal collection and storage, this paper designed a 12 bit100 Ms/s of the data acquisition system. The system USES the PCI bus are connected to the computer, the large capacity data acquisition s

24、ystem by using the interface card information useful for real-time information processing, data acquisition system external signal control. 2. Framework, Data acquisition card The whole collection system is divided into the following four parts: Part analog signal modulation, The clock processing mo

25、dule, Data caching module, Data transmission and trigger module. As shown in figure 2. 通信工程专业数据采集系统中英文资料外文翻译文献 figure 2 2.1 Analog signal modulation Analog signal modulation, including: before the analog signals and signal numerical control gain, and single side slip distribution. Analog signal pre

26、op-amp input signal of the impedance matching is realized by using AD9631 low-pass filtering and signal. In a radar system, scanning the target and radar stations from different collected radar signal amplitude is different, and in order to improve the signal-to-noise ratio of the acquisition system

27、, should make the simulation of the ADC input signal amplitude is close to full extent. So after pre op-amp added a voltage-controlled gain operational amplifier AD603 chips, to adjust the range of the ADC input signal. Voltage controlled gain AD603 chips under the analog bandwidth of 90 MHz, its sc

28、ope of gain - 11 dB 30 dB. The voltage controlled gain control voltage of the chip is produced by a 8 bit DAC, DAC chip select MAX503 MAXIM company, the digital input is produced by the FPGA control and chips. Data acquisition system of the ADC 12 bit chip AD9432 100 MHz of AD company, the analog si

29、gnal is 45 MHz still has a signal-to-noise ratio of 65 dB. Due to the ADC analog signal for the differential input, as a result, from the voltage controlled gain AD603 chips after a single-ended output analog signals difference AD8138 chip is connected to the ADC chip, from 12 bit ADC output digital

30、 signal directly connected to the FPGA chip. 通信工程专业数据采集系统中英文资料外文翻译文献 2.2 RTC In order to increase the acquisition systems flexibility and universality, the ADC sampling clock chip can be from an external clock, also can from the internal clock. The choice of the sampling clock is decided by the boar

31、d jumper wire device. Through a SMA connector is connected to the external clock collection on the board, the external clock signal into TTL level, due to the ADC sampling clock need to PECL level, therefore the external clock by TTL to PECL level conversion chip MClOELl6 selection module connected

32、to the clock. The ADC internal clock is produced by CNC clock module of the system. NC SY89429 clock module selection frequency synthesizer. The device clock output in the range of 25 MHz to 400 MHz, the output signals for PECL, can be directly connected to the ADC sampling clock. The clock output o

33、f the frequency synthesizer can be controlled and the 11 digital signal chip, can accurate to adjust the output clock precision l MHz. 11 digital signal is controlled by FPGA. In a data acquisition system, especially in high speed data acquisition system, the clock is a very important letter.Differe

34、nt clock jitter are relatively large. When the input analog signal acquisition system bandwidth is greater, the clock jitter on signal-to-noise ratio of the acquisition system cannot be ignored. The quantization noise factors into consideration also 1, right In the 12 bit ADC, when the input signal

35、frequency is 40 MHz, signal-to-noise ratio and the sampling clock jitter curve as shown in figure 3, the abscissa of sampling clock jitter, y coordinate for the signal-to-noise ratio of the acquisition system. Can be seen from figure 3, to make ADC acquisition system signal to noise ratio greater th

36、an 50 dB, sampling clock jitter must be controlled within 10 ps, otherwise, the SNR loss caused by the external clock jitter will degrade the performance of the AD9432. SY89429 chip is applied in this system, the output clock jitter peak maximum 25 ps, clock jitter RMS for around 10 ps, meets the de

37、sign requirements of the system. If you want to use the external clock, must choose to have low jitter of the external clock source. 通信工程专业数据采集系统中英文资料外文翻译文献 figure 3 2.3 High speed data cache module High-speed ADC data storage is a Cyclone FPGA chip by A1tera company control. Logical structure as sh

38、own in figure 4 figure 4 Data acquisition system using MT48LC4M16A2SDRAM parallel 2 tablets up to MICRON company as a system of on-chip memory. Parallel SDRAM memory bits wide is 32 bit, the capacity of 16 MB, the clock frequency of 100 MHz. Than SRAM chip SDRAM chips have higher working speed, larg

39、er capacity, provides more flexibility for system design. In order to improve the transmission bandwidth of SDRAM, the breaking length of SDRAM controller (burst length) at eight The burst length is in addition to the full page read/write the biggest burst length. From high-speed 12 bit ADC come ove

40、r 100 MHz signal at the trigger 通信工程专业数据采集系统中英文资料外文翻译文献 enabling signal is valid, written by deposit of the ADC data flow control module to extend the l times, extended 24 bit sampling data to save FIF0. When memory read control module detects that the storage data in FIF0 depth gets 8, read from th

41、e remaining FIFO 8 and 24 bit data,And use the wishbone (wb) 14 bus data transfer to the SDRAM controller, by the data to the external SDRAM chip SDRAM controller. Although external SDRAM chip data bus width is 32 bit, but the actual use of only 24 bit, namely theory of SDRAM bus transmission bandwi

42、dth is 300 MB/s. Considering the SDRAM to refresh and sudden transmission overhead, actually can achieve 200 MB/s, and the ADC sampling data transmission bandwidth is 150 MB/s, therefore, is enough to satisfy the real-time sampling data storage SDRAM controller. FIF0 has a capacity of 2 KB, wide is

43、24 bit. Due to the actions include SDRAM refresh, read and write operations, sudden sudden from storage control module output data is not stored in real-time SDRAM, so use save FIF0 complete data storage speed matching and data store within the FPGA chip. Memory read control module is responsible fo

44、r the SDRAM controller by sudden writes, Because the SDRAM controller adopts the burst transmission operation, so every time control module must be transmitted to SDRAM memory read a piece of sampling data (16),This requires ADC transfer the amount of data that must be in multiples of 16, also confo

45、rms to the actual demand. In order to improve the transmission performance of wb write bus, memory read once control module detects that the storage amount of data in the FIFO is greater than or equal to a block, start the wb write bus operation. In the entire data acquisition system, SDRAM is store

46、d in the form of circular sampling data, improve the efficiency of the use of SDRAM, simplifies the logic design of the system. 2.4 Data transmission and trigger module Using AMCC company s5933 PCI master devices transmit the sampled data to a computers memory. S5933 is a kind of special function is

47、 very strong, flexible use of PCI bus controller chip. It completely conforms to the PCI local bus specification 2.1 l, from already can do PCI bus device, and can do PCI bus master device for data transmission. S5933 have three interfaces: PCI bus interface, ADDON bus interface and external NVRAM p

48、arameters 通信工程专业数据采集系统中英文资料外文翻译文献 configuration interface. The PCI bus interface and the computer connected to the PCI bus slot. Computer and user can through the ADDON bus interface of FIF0 channel and PATH - THRU channel to communicate with each other. PCI bus by using PATH. THRU channel and clien

49、t information interaction. Client using FIFO channel to local store data through the computer PCI bus to the computer memory. Computer using s5933 PASS. TRU operation control of the FPGA internal registers. When computer PCI address on PASS - THRU define a zone, s5933 to the PATH of the FPGA - throu

50、gh PTATN TRU and decoding logic control request. PATH - TRU and decoding logic control according to determine the operating PATH - PTADR signals TRU to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PATH - TRU internal

51、 registers). The FPGA using PATH - THRU address information for the corresponding decoding operation, strobe internal different registers. Computer using s5933 PASS. TRU operation control of the FPGA internal registers. When computer PCI address on PASS - THRU define a zone, s5933 to the PATH of the

52、 FPGA - through PTATN TRU and decoding logic control request. PATH - TRU and decoding logic control according to determine the operating PATH - PTADR signals TRU to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PATH -

53、 TRU internal registers). The FPGA using PATH - THRU address information for the corresponding decoding operation, strobe internal different registers.： (1) according to the biggest computer to analog signals collected, through nc gain DAC register ADC input analog signal input is close to full ampl

54、itude. (2) through the ADC sampling clock registers set ADC sampling clock working (if using the internal clock frequency. (3) set the ADC to gather the amount of data: data volume for 32-bit registers, enough to meet the needs of the existing radar system, the total data registers must be a multipl

55、e of 16. (4) through the pattern configuration register setting the operation mode of the ADC high-speed data acquisition system: set up the ADC external trigger signal trigger mode (level trigger or edge-triggered), set up the ADC sampling signals to trigger software or hardware 通信工程专业数据采集系统中英文资料外文

56、翻译文献 trigger (that is, the external trigger), can control the ADC sampling. (5) sets the trigger delay period: radar system the trigger delay time of sampling time can be set through the register Trigger module according to the trigger condition, the number of sampling data amount and single trigger

57、 sampling trigger enabling signal, the signal is equivalent to save FIF0 write enable signal. Computer using s5933 PCI main module FIF0 channel automatic transmission to realize sampling data to the computers memory. S5933 FIF0 channel within the write operations performed by FPGA, the read operatio

58、n performed by internal controller s5933. Once detected s5933 WRFULL transcription control module (F1F0 channel full signals) is invalid, or PCI main module to write FIF0 channels is not full, the double clock FIFO reads data from the airborne, and the data written to the s5933 PI main module FIFO w

59、ritten passages. Cache block number record SDRAM controller inside how much a data block to be transmitted, in to write a block of data, the SDRAM cache block number l, when read a block of data from SDRAM, cache blocks is minus l. Double clock FIFO capacity of 2 KB, rate matching and data buffer im

60、plementation, speaking, reading and writing. Preach dual clock FIFO write control by read complete control logic. The read only in data transmission to complete control logic and the double clock FIF0 is not full to launch wb bus read operation, read a block of data from SDRAM buffer and referring t

61、o the data block into the dual clock FlF0. Wishbone bus arbitration module realizes the wb write bus and wb bus arbitration, and read it with the method of fixed priority, wb write bus priority than wb read bus priority, guarantee the real-time sampling data stored locally. 3. Software design In ord

62、er to improve data transmission rate and reducing the number of CPU resources, data acquisition is realized by using PCI master way of data to the computers memory. However because of s5933 single chip 64 MB, the maximum amount of data transferred so if you want to Continuous transmission is larger

63、than 64 MB of data, then need to start the main 通信工程专业数据采集系统中英文资料外文翻译文献 mode data transmission for many times. In the process of data transmission, the CPU does not carry on the process control. Software to perform PCI bus scan first, obtain s5933 PCI configuration space occupied chip address, and t

64、hen apply to the operating system for gathering data is passed to the physical space of the computers memory, and the address is mapped to a physical space s5933PCI main devices. Then software configuration S5933 chip internal registers, including the DMA transfer data amount and PCI bus transmission characteristics such as register, and can make s5933PCI master operation. S5933 waiting for FPGA to send data, if s5933 Internal write FIFO chip channel is not empty, are launching PCI bus operation pass data to the computer memory.Software through s5933 PASS to TRU according to the requirements