计算机组织与结构：Ch_3 System Buses

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1、William Stallings Computer Organization and Architecture7th EditionChapter 3System BusesProgram Concept Hardwired systems are inflexible General purpose hardware can do different tasks,given correct control signals Instead of re-wiring,supply a new set of control signalsWhat is a program?A sequence

2、of steps For each step,an arithmetic or logical operation is done For each operation,a different set of control signals is neededFunction of Control Unit For each operation a unique code is providede.g.ADD,MOVE A hardware segment accepts the code and issues the control signals We have a computer!Com

3、ponents The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results outInput/output Temporary storage of code and results is neededMain memoryComputer Components:Top Level ViewInstruction Cycle Two steps:Fetc

4、hExecuteFetch Cycle Program Counter(PC)holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PCUnless told otherwise Instruction loaded into Instruction Register(IR)Processor interprets instruction and performs required actionsExecut

5、e Cycle Processor-memorydata transfer between CPU and main memory Processor I/OData transfer between CPU and I/O module Data processingSome arithmetic or logical operation on data ControlAlteration of sequence of operationse.g.jump Combination of aboveExample of Program ExecutionInstruction Cycle-St

6、ate DiagramInterrupts Mechanism by which other modules(e.g.I/O)may interrupt normal sequence of processing Program e.g.overflow,division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O from I/O controller Hardware failure e.g.memory parity errorProgram Flow

7、ControlInterrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt,fetch next instruction If interrupt pending:Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Resto

8、re context and continue interrupted programTransfer of Control via InterruptsInstruction Cycle with InterruptsProgram TimingShort I/O WaitProgram TimingLong I/O WaitInstruction Cycle(with Interrupts)-State DiagramMultiple Interrupts Disable interruptsProcessor will ignore further interrupts whilst p

9、rocessing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occur Define prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed,processor r

10、eturns to previous interruptMultiple Interrupts-SequentialMultiple Interrupts NestedTime Sequence of Multiple InterruptsConnecting All the units must be connected Different type of connection for different type of unitMemoryInput/OutputCPUComputer ModulesMemory Connection Receives and sends data Rec

11、eives addresses(of locations)Receives control signals ReadWriteTimingInput/Output Connection(1)Similar to memory from computers viewpoint OutputReceive data from computerSend data to peripheral InputReceive data from peripheralSend data to computerInput/Output Connection(2)Receive control signals fr

12、om computer Send control signals to peripheralse.g.spin disk Receive addresses from computere.g.port number to identify peripheral Send interrupt signals(control)CPU Connection Reads instruction and data Writes out data(after processing)Sends control signals to other units Receives(&acts on)interrup

13、tsBuses There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g.Control/Address/Data bus(PC)e.g.Unibus(DEC-PDP)What is a Bus?A communication pathway connecting two or more devices Usually broadcast Often groupedA number of channels in one buse.g.

14、32 bit data bus is 32 separate single bit channels Power lines may not be shownData Bus Carries dataRemember that there is no difference between“data”and“instruction”at this level Width is a key determinant of performance8,16,32,64 bitAddress bus Identify the source or destination of data e.g.CPU ne

15、eds to read an instruction(data)from a given location in memory Bus width determines maximum memory capacity of systeme.g.8080 has 16 bit address bus giving 64k address spaceControl Bus Control and timing informationMemory read/write signalInterrupt requestClock signalsBus Interconnection SchemeBig

16、and Yellow?What do buses look like?Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boards e.g.PCISets of wiresSingle Bus Problems Lots of devices on one bus leads to:Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggr

17、egate data transfer approaches bus capacity Most systems use multiple buses to overcome these problemsTraditional(ISA)(with cache)High Performance BusBus Types DedicatedSeparate data&address lines MultiplexedShared linesAddress valid or data valid control lineAdvantage-fewer linesDisadvantages More

18、complex control Ultimate performanceBus Arbitration More than one module controlling the bus e.g.CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributedCentralised Arbitration Single hardware device controlling bus accessBus ControllerArbiter

19、May be part of CPU or separateDistributed Arbitration Each module may claim the bus Control logic on all modulesTiming Co-ordination of events on bus SynchronousEvents determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on

20、leading edgeUsually a single cycle for an eventSynchronous Timing DiagramAsynchronous Timing Read DiagramAsynchronous Timing Write DiagramPCI Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 linesPCI Bus Lines(required)Systems linesIncluding clock and reset Ad

21、dress&Data32 time mux lines for address/dataInterrupt&validate lines Interface Control ArbitrationNot sharedDirect connection to PCI bus arbiter Error linesPCI Bus Lines(Optional)Interrupt linesNot shared Cache support 64-bit Bus ExtensionAdditional 32 linesTime multiplexed2 lines to enable devices

22、to agree to use 64-bit transfer JTAG/Boundary ScanFor testing proceduresPCI Commands Transaction between initiator(master)and target Master claims bus Determine type of transactione.g.I/O read/write Address phase One or more data phasesPCI Read Timing DiagramPCI Bus ArbitrationForeground Reading Stallings,chapter 3(all of it) fact,read the whole site!