单片机设计外文翻译---- 单片机工作原理

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1、附 录一、英文原文:The Principle of Microcontroller In operation the Single Chip Microcomputer (SCM)is connected to a host PC microcomputer via aserial port. The connecting cable is included with the unit. The SCM is supplied fitted with an 8751 chip. This chip features internal ROM containing versatile,real

2、 time monitor to communicate with a PC via the built-in serial port. The monitor includes a line assembler, disassembler, break points, single stepping and the facility to examine and exchange memory or register contents. A special function of the monitor is to store the program under development in

3、 the RAM of the SCM development board. The great advantage of the method that is direct access to the I/O ports is provided by the 8051 is retained and, consequently,the need for a costly in-circuit-emulation (ICE)package is not required. Once a program has been completed on the SCM development syst

4、em it can be easily transferred intothe ROM of another 8751 via an EPROM programmer. This second 8751, now containing the control program, can be removed from the Programmer and installed into the SCM-TB target board. Most importantly, because direct access to the input/output ports of the 8751 has

5、been retained during the development stage there is no need for peripheral I/O and address decoding chips; only the8751 chip is required. Thus the Single Chip Micro-Control, not multi-chip control is realised. The SCM-TB target board feature a single 40-wayDIL socket for the micro-controller chip pl

6、us termination facilities identical to the SCMDevelopment Board for simple and convenient transfer of any connecting cables. 8751 ICS should be purchased separately for the target board.In addition to the Single Chip Development System and Target Board, a number of add-on boards are available. These

7、 include a Port Monitor Board,Multi-Channel ADC, Screw Terminal Board andOutput Driver Board. Voice input to a machine is the most natural form of man-machine communications. Research coming to fruition overthe past several years indicates that the techniques of manmachine communication by voice con

8、stitute a whole new range of communication servicesservices that can extend mans capabilities, serve his social needs, and increase his productivitySpeech recognition can be defined as the technology which makes it possible for a computer to accept voice dataas input and then identify the word or ph

9、rases. There is atwofold rationale for a speech-recognition systea:(1) It is an easier means for noncomputer professionals toenter data into the computer.(2) In certain applications, such as in semiautomatedquality-control inspection procedures, computer usersneed to use their hands for other tasks.

10、 Speech recognition is a part of a broader speech processingtechnology involving computer identification or verification of speakers, computer synthesis of speech, production ofstoredspokenresponses,computer analysis of the physicaland psychological state of the speaker, efficienttransmission of spo

11、ken conversations, detection of speechpathologies, and aids to the handicapped , taking machinestalk and listen to humans depends upon economical implementationof speech synthesis and speech recognition.A number of different feature sets have been proposedto represent speech signals; these include e

12、nergy and zerocrossing rates, formant filtering, short time spectrum,waveform digitization and linear predictive coding (LPC).The motivation for choosing one feature set over another isoften complex and highly dependent an constraints imposedupon the system, e.g., cost, speed, response time, computa

13、tionalcomplexity, etc- Of all the many available feature sets, linear predictive coding is usually the most effectiveone . There are many classifications for computers, ranging from inexpensive microcomputers used in homes and offices, to liquid-cooled supercomputers used in universities and researc

14、h laboratories. The present invention relates to microcomputers, also known as personal computers (or PCs). A microcomputer can be defined as a computer having a mass-produced integrated circuit microprocessor, such as, for example, the Intel 8086 family of products which presently includes the 8086

15、, 80286, 80386 and 80486 microprocessors. Although the microprocessor is the heart and defining feature of a microcomputer, it is not very useful unless it is integrated with a memory and a set of input/output (I/O) devices, also known as peripherals. These three classes of devices communicate among

16、 themselves over a shared set of digital signal lines called a bus. The bus is logically organized into sets of address, data, and control lines. The address lines are for communicating device addresses which uniquely identify a particular device on the bus. The data lines are for communicating bina

17、ry data between two bus devices, a bus master, which initiates a data transfer by placing an address on the address lines, and a bus slave, which reads and decodes the address generated by the bus master as its own. The control lines are for coordinating access to the bus and selecting a mode of ope

18、ration on the bus such as write data or read data modes. For example, if the bus master is a microprocessor and the bus slave is a memory, the microprocessor may direct thememory to be read by placing the proper logic level on a write/read control line. In this way, the microprocessor gains access t

19、o the data stored in the memory location specified by the logic levels placed on the address lines by the microprocessor. A bus cycle begins when the bus master directs a write or a read on the bus. The bus cycle is completed after all data has been transferred across the bus and the bus master rele

20、ases control of the bus. If the two devices communicating with each other over the bus operate at the same speed, then a bus cycle may be achieved over a minimum number of clock cycles. If, on the other hand, a bus device can only transmit or receive data over many clock cycles, then a delay must be

21、 injected into the state sequencing of the faster device. In such cases, a ready control line is typically activated by the slower device to indicate to the faster device that data is available on the bus or has been taken from the bus. Buses may be generally classified as synchronous or asynchronou

22、s, where synchronous buses are distinguished by the requirement that all bus devices synchronize their use of the bus by a single clock source (or a fundamental frequency). An example of a synchronous bus used in a microcomputer is the IBM PC AT I/O Channel, AT-bus or Industry Standard Architecture

23、bus (ISA-bus). Present bus frequency standards for the ISA-bus are 8 MHz and 10 MHz. The ISA-bus, an example of a synchronous bus, is used with the Intel 80386 microprocessor. The ISA-bus provides a 16-bit data bus and a 24-bit address bus. For purposes of this discussion, the control lines of the I

24、SA-bus include four bus cycle definition lines. The bus cycle definition lines define the type of bus cycle being performed. (In the following definitions, and throughout the remainder of this patent document, all signal names that are terminated with an asterisk * indicate an active low signal). A

25、bus cycle definition line called memory read (MEMR*) is active when data is to be read from memory. A bus cycle definition line called memory write (MEMW*) is active when data is to be written to memory. A bus cycle definition line called I/O read (IOR*) is active when data is to be read from a peri

26、pheral device. A bus cycle definition line called I/O write (IOW*) is active when data is to be written to a peripheral device. In addition to the above-mentioned bus cycle definition signals there are some microprocessor specific signals that are used in most microcomputers for specifically interfa

27、cing the Intel 8086 microprocessor family. There are two bus control signals and two bus arbitration signals of particular importance for bus interfacing. The bus control signals allow the microprocessor to indicate when a bus cycle has begun, and allows other bus devices to indicate a bus cycle ter

28、mination. The address status (ADS*) signal indicates that a valid bus cycle definition, and address, is being driven at the output pins of the 80386 microprocessor. The transfer acknowledge (READY*) signal indicates that the current bus cycle is complete. One skilled in the technology will understan

29、d the operation of the ISA-bus, other applicable industry standard buses, and the Intel 8086 microprocessor family. At least two references are available on the subject including The IBM PC from the Inside Out, Revised Edition, by Murray Sargent III and Richard L. Shoemaker; and IBM PC AT Technical

30、Reference published by IBM Corporation. Synchronous buses are ordinarily preferred for microcomputers since they can often transfer data faster than asynchronous buses. Certain applications, however, especially where lengthy communication distances are involved, require asynchronous or handshake onl

31、y type buses. When devices are separated by some distance, the same phase transition of a common clock cannot be guaranteed. The primary disadvantage of the synchronous ISA-bus has only recently been recognized. Basically, microcomputers are evolving down two separate paths of variables: one set of

32、variables is associated with the bus design and the other set is associated with the microprocessor and memory designs. A synchronous bus, such as the ISA-bus, should remain constant so that microcomputers in a single product line are all compatible. That is, a peripheral such as a modem, printer an

33、d so on will operate through a respective controller at the clock frequency defined in the bus specification. Therefore, the bus should only change through more efficient (i.e., cost effective) designs which meet the same specifications. For example, the operating frequency of the bus should remain

34、constant to assure proper operation of all peripherals constructed in accordance with the bus standard. In contrast, microprocessor and memory technologies are rapidly evolving in functionality and performance. For example, the microprocessor changes in architectural definition (e.g., number of pins

35、, instruction sets, etc.) and clock frequency (e.g., 16 MHz, 25 MHz, 33 MHz), the cache becomes more sophisticated, coprocessors become a part of the microcomputer architecture (e.g., Intel 80387 numeric coprocessor), and main memory becomes faster. As an example of memory evolution, consider dynami

36、c random access memory, or DRAM. As DRAM technology improves, the opportunity for improved system performance becomes clear. In the early days of personal computers, the common DRAM chip being used in microcomputers was 64K1 (65,5361 bits), having an access time of 150 nanoseconds. Recently, a stand

37、ard (i.e., readily available and cost effective) DRAM size used by microcomputer manufacturers was 256K1, having an access time of 100 nanoseconds. Presently, a DRAM chip standard of 1M1 (i.e., 1,048,5761 bits), having an access time of 80 nanoseconds or less is evolving as a commercially feasible s

38、tandard, and the technology trend is toward a 16M by 1 bit chip. It is desireable to isolate the memory and microprocessor from the synchronous I/O bus design so that different DRAM and microprocessors at different operating frequencies can be used without affecting the synchronous I/O bus design. O

39、therwise, if the synchronous bus is not isolated from the computation and storage elements, each technological improvement in memory or microprocessor products will require unique interface circuitry to scale-down communication speed with other devices across the synchronous bus. Consequently, a nee

40、d exists for improvements in microcomputer systems to isolate I/O channel design from memory and microprocessor designs. 二、英文翻译： 单片机工作原理 在通过端口把单片机连接到个人电脑上的操作中连接电缆也包含在这个系统中。 单片机安装有一个8751芯片,这个芯片内部的ROM包含多种功能.实时监控器通过PC的串行端口进行联系。监控器包含一个行汇编，反汇编，断点，单步和检验及存储器、存放器间内容进行交换的设备。 监控器的一个特殊功能是存储单片机开发板RAM中的程序。该方法的优点

41、是直接进入到由8051保存的I / O端口，因此，一个昂贵的电路仿真ICE包是不必需的。 一旦单片机开发系统方案已经完成便可以轻松地通过一个EPROM将程序转移到另一个8751ROM。第二个8751芯片现在包含控制程序，可以从程序编程器中移除并且安装到单片机。最重要的，因为直接访问输入/输出端口的8751一直保存在开发阶段，因此外围I / O和地址解码芯片是不需要的，只有8751芯片是必需的。因此，单片机控制，不是多芯片控制得以实现。 单片机集成板的特点为微控制器芯片与单片机的终端设备都为40 wayDIL插座。板子的开发为电缆连接更加简单方便。8751 ICS应该是单独购置。除了单片机开发系

42、统和目标板，一系列附加板子是单独提供的这些包括端口显示器，多通道ADC，螺丝终端板和输出驱动板。 将语音输入到一台计算机是人机通信最原始的形式。过去几年来的研究成果说明，通过声音进行人机通信的技术成为了一项全新的通信效劳技术，这项效劳可以提高人的能力，为社会效劳，并提高生产力。 语音识别可以被定义为一种把声音数据作为输入并能区分单词和语法的技术。语音识别系统有两方面的优点：1它是一种非常简单的技术手段，非专业的计算机人员也可以把数据输入电脑。2在某些应用方面，如半自动质量控制检查程序，计算机用户需要去做其它方面的任务。语音识别是更广泛的语音处理技术的一局部，它涉及电脑技术鉴定或对语音输入的核实

43、，电脑语音合成，对已存储语音的反响，计算机的物理分析和对声音输入者心理状态的分析，高效率传输口语对话，语音检测，采取机器语言，并听取人类的口令依靠的是综合语音应用系统和语音识别。表达语音信号的许多不同特征已经被提出。这些包括能源和零交叉率，共振峰滤波，短时谱，波形数字化和线性预测编码LPC等。选择一个功能较另一组的动机往往是很复杂的，它受限于系统。如本钱，速度，反响时间，电脑的复杂程度等-所有可以考虑的特征。 有很多分类的计算机，从家庭和办公室使用的廉价的微型计算机，到在大学和研究实验室使用的液体冷却的超级计算机。本创造涉及微型计算机，也称为“个人电脑。 微机可被定义为一个“由一个大规模的集成

44、电路组成的微处理器，例如英特尔80 86的产品家族，目前包括8086，80286，80386和80486微处理器。虽然微处理器是微机的核心和主要特征，但它不是很有用，除非它和内存还有输入输出端口集成在一起，这三类设备间进行通信是在一个共享的数字信号线上称为总线。 总线在逻辑上是由一系列的地址，数据和控制线构成。地址线是在总线上唯一被确定的通信设备的地址。数据线是在两个总线设备间传送二进制数据，总线主机是通过放置地址总线的一个地址进行数据转换，总线附属是读取和解码。把总线主机产生的地址作为自己的地址。控制总线是协调总线入口和选择一个操作总线的适宜模式，例如数据输入模式和数据读出模式。例如，如果总

45、线主机是微处理器，总线附属是一个内存，微处理器的内存可直接被读出通过在读写控制线上找寻适宜的逻辑电平。这样，微处理器能够访问由微处理器的地址线的逻辑电平确定的存储单元中存储的数据。当总线主机开始在总线上的读写时一个总线周期便开始了。当所有数据在总线上翻译后总线周期释放了对总线的控制一个总线周期便完成了，如果两个设备通过总线操作以相同的速度进行通信，那么总线周期可能会用最小的周期。如果，另一方面，总线设备只能发送或接收数据的时钟周期，那么速度相对较快的设备必须进行延迟。在这种情况下，已经就绪的控制线通常是由慢的装置启动然后指示相对较快的设备总线可以使用或已经从总线接受了数据。总线一般可划分为同步

46、或异步，同步总线是由同一时钟源下所有总线设备同时使用总线来区别的或根本频率。微机中一个同步总线的例子是IBM个人电脑的I / O通道。目前总线的ISA总线频率标准是8兆赫和10兆赫。 ISA总线，同步总线一个的例子，用作Intel 80386的微处理器。在ISA总线提供了一个16位数据总线和24位地址总线。对于本次讨论目的，ISA总线的控制线，包括4个总线周期的定义线。该总线周期定义线定义了总线周期的类型。 当数据从内存中读出时一个总线周期定义线调用内存读取“MEMR *。当总数据被写入内存时一个总线周期定义行调用存储器写“MEMW *。当数据从外围设备读入时一个总线周期定义行调用I / O读

47、“提高采收率*。当数据写入外围设备时一个总线周期定义行调用的I / O写。 除了上述总线周期定义信号，还有一些用于大多数微机专门接口的英特尔处理器的80 86系列微处理器的特定信号。有两种总线控制信号和两种对总线接口尤为重要的仲裁信号。当总线周期开始的时候总线控制信号允许微处理器给出指示。地址状态信号说明，一个有效的总线周期的定义和地址由80386微处理器的输出引脚驱动。当转移确认“待用*的信号时说明当前总线周期完成。 一个熟练掌握这项技术的人将了解ISA总线的运行，其他适用的行业标准总线，以及80 86的英特尔微处理器家族，至少两个都可以用于这个课题的参考，包括有 Murray Sargen

48、t III 和 Richard L. Shoemaker出版的修订版还有由IBM公司出版的IBM电脑技术参考。同步总线通常首选微型计算机，因为它的数据传输速度比异步总线快。但是，某些应用尤其是长距离的通信，需要异步或“握手式的总线。当设备被分开一段距离，时钟同相变不能得到保证。 同步ISA总线的主要缺点最近才被认识到。根本上，微型计算机正在形成两条不同路径的变量：一组变量是与总线的设计和其他与微处理器和存储器的设计相关的设置。一个同步总线，如ISA总线，应保持稳定，以便使微机在单一的生产线上兼容。也就是说，外围设备如调制解调器，打印机将通过在总线定义下的时钟频率控制器下运行。因此，总线应通过符

49、合相同标准的更有效的设计进行改变。例如，总线的工作频率应保持不变，以保证所有外围设备正确操作与总线标准一致。 相比之下，微处理器和存储技术的性能和功能正在迅速开展中。例如，微处理器在结构定义方面的变化例如，引脚数，指令集等和时钟频率例如，16兆赫，25兆赫，33兆赫，缓存变得更加复杂，协处理器成为微机体系结构的一局部例如，英特尔80387数字协处理器，主内存变得更快。作为内存开展的例子，考虑动态随机存储器，或“内存。随着DRAM技术的开展，为提高系统性能的时机就很清楚了。在个人电脑开展的初期，微型计算机用的是64K的 165,536 1位的动态随机存储器，有1 150纳秒存取时间。最近，一个标准内存大小256K的微机制造商使用的是 1，有1 100纳秒存取时间。目前，一个标准的80纳秒或更少的存取的1M*1DRAM芯片正在演变为一个商业上可行的标准，而技术趋势是1600万的一位芯片。 把内存和微处理器从同步输入输出端口总线设计中别离出来是可取的，这样在不同操作频率下工作的不同的动态随机存储器和微处理器可以在不影响同步输入输出端口总线设计的情况下使用。否那么，如果同步总线没有从计算和存储单元中别离，每个存储器或微处理器技术的进步都需要特有的接口电路，用来扩展同步通信总线上的其他设备的速度。因此，微机系统中把输入输出端口通道设计和存储器还有微处理器设计别离开来是必要的。