StaticTimingAnalysisSTAPPT优秀课件

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1、Static Timing AAgendaPRE-REQUISTES:Knowledge of Digital Design TOPICS COVERED:-Basic STA concepts-Basic Primetime Commands,Interpretaion of Primetime reports-Advanced STA(Mutliple clocks,Latches,OCV)-Setting up Primetime(Appendix 1)What is Static timing Analysis?What is static Timing Analysis(STA)?I

2、t is a method to determine if a circuit meets timing constraints without simulation.Why Static Timing Analysis?100%path coverage is possible because no design specific pattern is required All paths are assumed critical Process variation across die can be modeled constraints and reports are concise a

3、nd easy to interpretPlace of STA in the ASIC FlowSPECSSPECSRTL CodingRTL Coding SynthesisGate level SimulationFloor planning/P&R/Timing Closure/Design ClosureFAB RTL RTL Simulation/VerificationSimulation/VerificationWireload models Chip Testing Back annotation(SDF)Cell Libraries Top Level Design and

4、 ArchitectureTop Level Design and Architecture Static Timing AnalysisDFT insertionConventional Front EndBack End DivideParasiticExtraction(SPEF)Phases of STA:Basic STA conceptsPre-Layout STAPost-Layout STAClock skewsIdeal clock assumed with estimated skewActual clock delays(Propagated clock)Net Dela

5、ysWire load modelParasitics (SPEF or SDF)UseTo verify the flow,for estimationFinal Sign offWireload Models Wire LoadsEstimate interconnect length Statistical Analysis of Previously Routed ChipsPredict the interconnect capacitance as a function of net fan-out and block size.Wire Load TableNet LoadNet

6、fanoutNetfanoutNet Resistance1230.0300.0600.04540.01510.01220.01630.02040.024Inputs&Outputs of STA Inputs Netlist(verilog):The gate level circuit description.Constraints(sdc/tcl):The design related data Net Delays Parasitics(SPEF):These are the parasitics of the design extracted from physical design

7、 tools.OR SDF:Standard Delay Format file containing back-annotated delays.Models(lib/db):The delay model of every cell in the library Outputs Reports:The timing paths report which can be used for debugging.Basic STA concepts Fundamental timing questions of a system Can design work at specified clock

8、 speed?STA tool calculates Arrival time(min/Early,max/Late)Required time(min/Early,max/Late)Slack Basic STA concepts:Timing PathsDQFF2DQFF1OUTPUTINPUTCLOCKTiming Point Each path has a startpoint and an endpoint Timing path Startpoints -Input ports,-Clock pins of flip-flops Timing path Endpoints -Out

9、put ports,-all input pins of flip-flops except clock pinsTypes of paths(I)FF1Setup timeSetup time:the time required for the data to be stable before the clock edge CLKD2FF2D1 Q1D2 Q2CLKLaunch EdgeCapture EdgeCombo logic54.5ns4.9setup violationCLK0setup time0.34.70.4nsHold timeHold time:the time requ

10、ired for the data to remain stable after the clock edgeCLK1D2=Q1FF1FF2D1 Q1D2 Q2CLK1Launch EdgeCQCLK20.3ns0.4CLK20.3hold time0.2Capture EdgeHold violation0.4ns0.5Setup and Hold timeSetup time:the time required for the data to be stable before the clock edge Hold time:the time required for the data t

11、o remain stable after the clock edgeCLKD2=Q1Q2FF1FF2D1 Q1D2 Q2CLKLaunch EdgeCapture EdgeCQCQhold timesetup timeData should change only within this windowSetup RequirementHold RequirementClk at FF21000Data at D pin of FF2Early Required TimeLate Required TimeSetup and Hold time in STAImportant!In STA,

12、Setup is checked at next edge and hold is checked at same edgeSetup Check Setup checkDQFF2DQFF1CALCULATION:Arrival time(max)=clock delay FF1(max)+clock-to-Q delay FF1(max)+comb.Delay(max)Required time=clock adjust+clock delay FF2(min)-set up time FF2Slack=Required time-Arrival time(since we want dat

13、a to arrive before it is required)clock adjust=clock period(since setup is analyzed at next edge)Hold check Hold check.CALCULATION:Arrival time =clock delay FF1(min)+clock-to-Q delay FF1(min)+comb.Delay(min)Required time=clock adjust+clock delay FF2(max)+hold time FF2 Slack=Arrival time-Required tim

14、e(since we want data to arrive after it is required)clock adjust=0(since hold is analyzed at same edge)DQFF2DQFF1Sections of a timing report HeaderData Arrival SectionData Required SectionSummary-SlackExample hold reportClocksSlew or Transition time:Time taken for a signal to reach from 10%of VDD to

15、 90%VDD10%90%SlewA clock is defined by its period,waveform and slew time.PeriodSlew riseSlew fallWaveform riseWaveform fallClocksJitter-Variation in period from clock source(PLL)clock skew=clock insertion delay of FF1 -clock insertion delay of FF2FF1FF2Insertion Delay delay from clock source to the

16、clock endpointSkew-Difference in arrival time at clock endpointsclkWill Skew affect setup and hold?What about jitter?Clocks Source latency and Network latencyPre vs Post Clock Tree Synthesis(CTS)Pre vs Post Clock Tree Synthesis(CTS)Test for Understanding(1)Test for Understanding(2)Master ClocksGener

17、ated clocks:Internally divided clocksDivided clocks(I)create_generated_clock-name DIVIDE-source get_ports SYSCLK-divide_by 2 get_pins FF1/QDivided clocks(II)create_generated_clock-edges 1 5 7 -name DIV3A-source get_ports SYSCLK get_pins U2/QVirtual ClocksVirtual Clocks Source latency and Network lat

18、encyBlockD QD QD QD QOn-block latency(network)Off-block latency(source)ClockConstraining the IOsInput DelayTest For UnderstandingCircle the:Input Delay constraintInput Port NameExternal start point clockOutput DelayTest For UnderstandingCircle the:Output Delay constraintWhy is there no library setup

19、 time in the Report?STA tools assume single cycle timing for all paths in design single cycle timing means that data propogates to its destination in less than one cycle timing exceptions are used to override the default single cycle constraints.False paths Multicycle paths Max delay Min delaymax_de

20、lay=1nsTiming ExceptionsFalse Paths False path-any logically false path-any register to register path which you do not wish to constrain-these paths are excluded from timing analysisMultiCycle Paths(I)Multi cycle pathfor setup:clock adjust time greater then one clock period for hold:clock adjust gre

21、ater then zero timeMultiCycle Paths(II)MultiCycle Paths(III)Case analysis(I)Case Analysis Functional/Test modes of the design specifying constant values or rise/fall transition at certain ports or pins.Example Test mode pinCase analysis(II)set_case_analysis 0 get_ports SCAN_MODEOther Timing Checks V

22、erified by STATypes of paths(II)PrimeTime:Path groupsPrimeTime implicitly creates a path group each time you use the create_clock command to create a new clock.clock_gating_default:paths that end on combinational elements used for clock gating async_default:paths that end on asynchronous preset/clea

23、r inputs of flipflops default:constrained paths that do not fall into any of the other implicit categories(for example,a path that ends on an output port)none:unconstrained pathsBasic STA concepts Recovery and Removal Recovery time is the minimum time that an asynchronous control must be stable befo

24、re the clock active-edge transition.Removal time is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.removal timerecovery timeclockasync_in Note:Asynch resets are synchronized before giving to CLRZ(reset)pin of flip-flopsGated clocksGated

25、clocksClock gating Setup check Enable of the clock to be stable before clock assertion,to preserve the waveformClock gating Hold check Enable of the clock to be stable after clock assertion,to preserve the waveform.Violation causes Glitch at the edge of the clock pulse.clipped clock pulseAZBEnableCl

26、ockOutclock gating holdclock gating setupclockEnableOperating Conditions Gate Delay depends on input slew output load strength of the gate Voltage temperature Sources of variation process variation(P)Supply voltage(V)Operating Temperature(T)Design cornersBest case (fast process highest voltage and l

27、owest temperature)Worst case(slow process lowest voltage and highest temperature)PVT Operating ConditionsTEMPERATUREPROCESSDELAYDELAYDELAY0 1.0 2.3 3.0 0 125 777777Maximum Operating Conditions-Worst CaseMinimum Operating Conditions-Best Case777777VOLTAGESetup and HoldDQQBTITEDQQBTITEscan enablefunct

28、ionalscan chain Most functional paths are long paths that make meeting timing during worst case operating conditions a challenge.Some functional paths,and many test paths,are very short,such as this scan chain.DQQBTITEDQQBTITEscan enable Early mode timing needs to be aware of both minimum and maximu

29、m timing.Clk(0ns)Clk(300ps)(0 slack MAX)(100ps)(350ps)Solution:Dont increase the loading of the Q output but use the unused QB outputSimultaneous Operating ConditionsOn-Chip VariationDQQBDQQBTEMP=60TEMP=65 On-chip variation is minor differences on different parts of the chip within one operating con

30、dition.On-Chip Variation On-Chip variation(OCV)delays vary across a single die due to variations in the maufacturing process(P),variations in the voltage(due to IR drop)and variations in the temperature(due to local hot spots etc.)This need to be modeled by scaling the coefficientsOn-Chip VariationO

31、CV DerationsTiming analysis with on-chip variation.For cell delays,the on-chip variation is between 5 percent above and 10 percent below the SDF back-annotated values.For net delays,the on-chip variation is between 2 percent above and 4 percent below the SDF back-annotated values.For cell timing che

32、cks,the on-chip variation is 10 percent above the SDF values for setup checks and 20 percent below the SDF values for hold checks.pt_shell read_sdf-analysis_type on_chip_variation my_design.sdfpt_shell set_timing_derate-cell_delay-min 0.90-max 1.05pt_shell set_timing_derate-net-min 0.96-max 1.02pt_s

33、hell set_timing_derate-cell_check-min 0.80-max 1.10 Common path pessimism It is possible to have common logic between min and max paths It is not possible to have two different delays simultaneously in a single gate or wire Common path pessimism removal removes common delays.CRPRPrimetime ReportPrim

34、etime slack report:Interpretation-Point Incr Path-clock CLK(rise edge)0.00 0.00clock network delay(propagated)-clock path delay of launch path(startpt)1.40 1.40 FF1/CP(FD2)0.00 1.40 r FF 1/Q(FD2)-CLK to Q delay 0.60 2.00 f BUF1/y(BUF)-combo delay upto the D pin of the endpt.register 3.20 5.20 f data

35、 arrival time 5.20clock CLK(rise edge)-includes Cycle adjust of 1 clock period 5.00 5.00 clock network delay(propagated)-clock path delay of capture path(Endpt)1.16 6.16 clock reconvergence pessimism-after correction for CRPR 0.16 6.32clock uncertainty-post cts this is only jitter -0.10 6.22 FF2/CP(

36、FD2)6.22 rlibrary setup time -0.20 6.02data required time 6.02-data required time 6.02data arrival time -5.20-slack(MET)0.82Path slack=required time-arrival time=(6.02-5.20)=0.82Multiple Clocks:SetupMultiple Clocks:HoldMultiple Clocks:Setup and Hold(I)Multiple Clocks:Setup and Hold(II)Setup Relation

37、ship:A Rising,B Rising Find the Setup Relationship between A rising and B rising:A(6 ns)08110237 B(8ns)459611 12 The setup relationship is the closest distance between the launching clock edge(A)and the receiving clock edge(B)13 14 15 16 17 18 19 20 21 22 23 2408110237459611 12 13 14 15 16 17 18 19

38、20 21 22 23 24DQQBDQQBBA8426Hold Relationship:A Rising,B Rising Find the Hold Relationship between A rising and B risingA08110237B459611 12 The hold relationship is the closest distance between the launching edge(A)and the previous receiving edge(B)13 14 15 16 17 18 19 20 21 22 23 2408110237459611 1

39、2 13 14 15 16 17 18 19 20 21 22 23 24DQQBDQQBBA6240Static Timing With Latches Latches DQQBDEQQBEE012345678 Latches are level sensitive instead of edge triggered Latches and Flip-Flops are both registers,or“storage devices”D012345678Q012345678Time BorrowingPHI1PHI2PHI1DQGDQGDQGPHI2051072 If these wer

40、e flip flops,timing would not be met at b_reg.With time borrowing,the middle latch can borrow time from the next stage and meet timing.15a_regb_regc_reg20Time Borrowing Example 2PHI1PHI2PHI1DQGDQGDQGPHI2051097No,the final data missed the active edge of c_reg.Q.Can time borrowing eliminate negative s

41、lack?a_regb_regc_reg1520Time Borrowing Example 3PHI1PHI2PHI1DQGDQDQGPHI2051056No,c_reg is a flip-flop and the data misses c_regs edgeQ.Can time borrowing eliminate negative slack?a_regb_regc_reg1520Time Borrowing Example 4PHI1PHI2PHI1DQGDQDQGPHI2051062Yes,in fact there is extra time before the activ

42、ating edge of c_reg.Q.Can time borrowing eliminate negative slack?a_regb_regc_reg15G20Time Borrowing Example 5PHI1PHI2PHI1DQGDQGDQGPHI20510111No.The earliest b_reg can launch the data is at time 5.c_reg will receive the data too late Q.Can time borrowing eliminate negative slack?a_regb_regc_reg1520L

43、atches:Time BorrowingLatches:Time BorrowingLatches:Time BorrowingConstraining Multiple-Mode Designs Multiple Mode Designs Same physical net may be part of two clocks The functional clock The test clock A mode input chooses which clock is propagated Timing optimization requires that Setup and hold vi

44、olations do not occur in test or functional mode Optimizer is aware of both modes concurrently optimizing only one mode at a time might fix a hold violation in one mode,only to cause a setup violation in the other.Constraints must expose all timing modes concurrentlyDQQBTEST_EN10TEST_CLKFUNC_CLKDQQB

45、DATA_INDATA_OUTSDscanscanSDSCAN_INSimple Clock Scheme for Multimode TEST_EN signal controls which clock to propagate.TEST_EN=1 means TEST_CLK will propagate.Scan chains are activated via the scan pins of registers.TEST_EN=0 means FUNC_CLK will propagate.Functional paths are activated via the data pi

46、ns of registers.Solution for Simple Multimode Scheme A simple multimode scheme allows the timer to be aware of the propagation of both clocks in the same run.This awareness enables single-pass implementation and optimization of both clocks and their associated timing paths.DQQBTEST_EN10TEST_CLKFUNC_

47、CLKDQQBDATA_INDATA_OUTSDscanscanSDSCAN_INThree Categories of ConstraintsMaster constraints file Contains most constraints for all modes of operationOverlapping clock exceptions file Contains constraints necessary to enable multiple modes to be visible in the same pass This file is read on top of the

48、 main constraints file in Magma for all implementation/optimization runs.Individual mode constraints files One file for each mode of operation In this example there are two(one each for test and functional modes).These files should not contain more than constant settings.These files are not used in

49、Magma for implementation/optimization.This type of file is read on top of the main constraints file in PrimeTime to set PrimeTime to a particular mode.The same is done in Magma for correlation-to-PrimeTime runs.The Master Constraints FileDefine both TEST_CLK and FUNC_CLKApply timing constraints for

50、all I/O and scan ports with respect to appropriate clockApply all other constraints as usual(drives,loads,slews,etc.)If multiple functional clocks can drive a given clock pin,choose the clock with the highest frequency and define that clock only This applies only to the case where the same boundary

51、clock pin might be driven by different clocks,depending on the mode.Do not declare all paths from/to either clock to be false,(Avoid open-ended false path statements on clocks).Do not set constants that choose either test mode or scan mode(Do not set TEST_EN high or low).DQQBTEST_EN10TEST_CLKFUNC_CL

52、KDQQBDATA_INDATA_OUTSDscanscanSDSCAN_INDQQBTEST_EN10TEST_CLKFUNC_CLKDQQBDATA_INDATA_OUTSDscanscanSDSCAN_INThe Overlapping CLK Exceptions File Declare the following as false:Paths from FUNC_CLK to all SD pins,if these paths cannot meet timing Paths from TEST_CLK to FUNC_CLK Paths from FUNC_CLK to TES

53、T_CLKDQQBTEST_EN10TEST_CLKFUNC_CLKDQQBDATA_INDATA_OUTSDscanscanSDSCAN_INPrimeTime Correlation-Mode AnalysisPrimeTime must perform mode analysis(set the design in a mode),because it cannot propagate multiple clocks on a net.For PrimeTime runs,you need one additional constraints file for each mode(mod

54、e constraints file)to set the design in a mode.For this simple example we need two files:test mode and func mode The test mode constraints file has the command:set_case_analysis 1 TEST_EN The func mode constraints file has the command:set_case_analysis 0 TEST_ENCombinational Loops DQQBDQQBBAZU0U1BAZ

55、Combinational Loop Example Most STAs cant leave combinational loops in the design,because a race condition will occur.1.1AT3.15.1 Magma STA training slides VSBU STA training ppt.Primetime user guide Primetime tutorial can be used for hands onReferences/Resources:Appendix 1Primetime Primetime Flow:Re

56、adandLinkDesignsandLibrariesSpecifyAttributes,Environment,Constraints,TimingExceptionsPerformAnalysis:ReportsandVisualanalysisPrimetime Setup Files:When primetime is invoked,it accesses.synopsys_pt.setup file in the following order Synopsys root directory the file provided by Synopsys contains gener

57、al setup information.User home directory-User can create this file for specific Primetime environment.Directory from which user starts Primetime(current working directory).User can create this file and customize it for a particular design.Setup the design environment:Set the search path and link pat

58、h.Read the Libraries and Design.Link the top design.Setup the operating conditions,wireload models,port load,drive and transition time.Primetime Specify the timing assertions(constraints)-Define clock period,waveform,latency and uncertainty.Specify input and output port delays.Specify timing excepti

59、ons-specify multicycle path specify false path Specify minimum and maximum delays specify disabled arcs.Perform analysis and generate reports Check timing Generate constraint reports Generate path timing reports Defining search path and Link path:notifies Primetime the files to use and where to use

60、them to perform Link process search path and link path are defined through primetime variable search_path and link_path respectivelye.g:set search_path “././lib”set link_path “*vendor_lib.db”Primetime Reading the Designs Primetime reads following design formats-Synopsys database files(.db)Verilog ne

61、tlist files Electronic Data Interchange Format(EDIF)netlist files VHDL netlist filese.g:read_db ./gtech/counter.db read_verilog./net/counter.v read_edif ./edif/counter.edif read_vhdl ./net/counter.vhdl Linking the Design link process resolves design references it loads libraries and designs specifie

62、d in the link_path variable if design is referenced and but was not explicitly loaded,linker attempts to load the design where the design is the referenced design-autoloadPrimetime Defining operating conditions ICs exhibit different performance under different operating conditions operating conditio

63、ns contains process derating factor(P),supply voltage(V),ambient temperature and interconnect model type delay calculation is affected by the operating conditions Setting Wireload Models predicts net capacitance and resistance after placement and routing net capacitance affects cell and net delays n

64、et resistance affects net delay wireload model is basically set of tablesnet fanout vs loadnet fanout vs resistancenet fanout vs area To access the timing of a circuit as accurately as possible WLM should be specified Since WLMs are used to model the effects of layout,they should be chosen carefully based on recommendation of your vendor a tree_type attribute in operating condition tells PT to model the net there are three possible tree types worst_case_tree(pessimistic),best_case_tree (optimistic),balanced_tree.个人观点供参考，欢迎讨论