组合逻辑电路进阶设计.ppt

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1、,第五章组合逻辑电路进阶设计,算术运算单元设计,ALU功能简介,ALU电路验证,逻辑运算单元设计,ALU功能简介,Entity的定义,Architechture的描述,2.算术运算单元设计,ENTITY adder IS PORT( A: IN UNSIGNED (3 DOWNTO 0); B: IN UNSIGNED (3 DOWNTO 0) Cin: IN STD_LOGIC; BCDout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) Cout: OUT STD_LOGIC ); END adder;,library IEEE; use IEEE.std_logic

2、_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity CH5_2_1 is port ( A : in UNSIGNED (3 downto 0); B : in UNSIGNED (3 downto 0); Cin : in STD_LOGIC ; S : in STD_LOGIC_VECTOR (2 downto 0) ; BCDout : out STD_LOGIC_VECTOR (3 downto 0) ; Cout : out STD_LOGIC ); end CH5_2_1

3、;,architecture ARCH of CH5_2_1 is SIGNAL C,Y : STD_LOGIC_VECTOR (3 downto 0) ; BEGIN PROCESS( S) BEGIN -*ADDER* case S is when 000 = Y(0) = A(0) XOR B(0) XOR Cin ; C(0) = (A(0) AND B(0) OR (B(0) AND Cin) OR (A(0) AND Cin); GEN1 : FOR I IN 1 TO 3 LOOP Y(I) = A(I) XOR B(I) XOR C(I-1) ; C(I) = (C(I-1)

4、AND A(I) OR (C(I-1) AND B(I) OR (A(I) AND B(I); END LOOP ; BCDout = Y(3) ,when 001 = -SUB ; Y(0) = A(0) XOR B(0) XOR Cin ; C(0) = (Cin AND NOT A(0) OR (Cin AND B(0) OR (NOT A(0) AND B(0); GEN2: FOR I IN 1 TO 3 LOOP Y(I) = A(I) XOR B(I) XOR C(I-1); C(I) = (C(I-1) AND NOT A(I) OR (C(I-1) AND B(I) OR (

5、NOT A(I) AND B(I); END LOOP ; BCDout = Y(3) ,when 010 = -TRANSFER A+Cin IF Cin=0 THEN BCDout = A(3) ,when 011 = -TRANSFER A-Cin ; IF Cin=1 THEN BCDout BCDout = 0000 ; Cout = 0; end case ; END PROCESS; end ARCH;,3.逻辑运算单元设计,library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use I

6、EEE.std_logic_unsigned.all; entity CH5_3_1 is port( A : in UNSIGNED (3 downto 0); B : in UNSIGNED (3 downto 0); S : in STD_LOGIC_VECTOR (2 downto 0) ; BCDout : out STD_LOGIC_VECTOR (3 downto 0) ); end CH5_3_1;,architecture ARCH of CH5_3_1 is signal Y: STD_LOGIC_VECTOR(3 downto 0) ; BEGIN PROCESS (A,

7、B,S) BEGIN CASE S IS when 100 = Y(3) Y(3) = A(3) or B(3) ; Y(2) = A(2) or B(2) ; Y(1) = A(1) or B(1) ; Y(0) = A(0) or B(0) ; BCDout = y(3),when 110 = Y(3) Y(3) BCDout = 0000 ; END CASE ; END PROCESS; end ARCH;,4.ALU电路验证,library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEE

8、E.std_logic_unsigned.all; entity CH5_4_1 is port ( A : in UNSIGNED (3 downto 0); B : in UNSIGNED (3 downto 0); Cin : in STD_LOGIC ; S : in STD_LOGIC_VECTOR (2 downto 0) ; BCDout : out STD_LOGIC_VECTOR (3 downto 0) ; Cout : out STD_LOGIC ); end CH5_4_1;,architecture ARCH of CH5_4_1 is SIGNAL C,Y : ST

9、D_LOGIC_VECTOR (3 downto 0) ; SIGNAL Q : UNSIGNED (3 downto 0) ; begin process(S) begin case S is when 000 =-ADDER ; Y(0) = A(0) XOR B(0) XOR Cin ; C(0) = (A(0) AND B(0) OR (B(0) AND Cin) OR (A(0) AND Cin); GEN1 : FOR I IN 1 TO 3 LOOP Y(I) = A(I) XOR B(I) XOR C(I-1) ; C(I) = (C(I-1) AND A(I) OR (C(I

10、-1) AND B(I) OR (A(I) AND B(I); END LOOP ; BCDout = Y(3) ,when 001 = -SUB ; Y(0) = A(0) XOR B(0) XOR Cin ; C(0) = (Cin AND NOT A(0) OR (Cin AND B(0) OR (NOT A(0) AND B(0); GEN2: FOR I IN 1 TO 3 LOOP Y(I) = A(I) XOR B(I) XOR C(I-1); C(I) = (C(I-1) AND NOT A(I) OR (C(I-1) AND B(I) OR (NOT A(I) AND B(I

11、); END LOOP ; BCDout = Y(3) ,when 010 = -TRANSFER A+Cin ; IF Cin=0 THEN BCDout -TRANSFER A-Cin ; IF Cin=1 THEN BCDout = A(3) ,when 100 = - AND ; Y(3) - OR ; Y(3) = A(3) or B(3) ; Y(2) = A(2) or B(2) ; Y(1) = A(1) or B(1) ; Y(0) = A(0) or B(0) ; BCDout = Y(3) ,when 110 = - XOR ; Y(3) - NOT ; Y(3) = NOT A(3) ; Y(2) = NOT A(2) ; Y(1) = NOT A(1) ; Y(0) = NOT A(0) ; BCDout = Y(3) ,when others = BCDout = 0000 ; Cout = 0; END CASE ; END PROCESS; end ARCH;,