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1、 信 息 工 程 学 院课 程 设 计 报 告题目：基于FPGA的智能电梯控制系统的实现Topic: INTELLIGENT ELEVATOR CONTROL SYSTEM 二 级 学 院 信 息 工 程 学 院 专 业 班 级 通 信 工 程2班 组 员 2014年 4 月 25日ABSTRACTIntelligent elevator compilation process is not easy. And I tried a variety of ways to realize the transfer of the state. At first I thought the affir

2、mation is a finite state machine. But due to start I thought only six request (respectively for 1 6 / f) and then in teacher inspired and east ten on the second floor of the elevator actual operation situation I found, 6 button affirmation is not enough, so I added five upward request button and fiv

3、e downward request button, so it has 16 button, because at that time I didnt think by signal and inverted method, so need analysis of true is too many, I also have no confidence. Nevertheless the problem are always to be solved, later I in our bedroom is a classmate of reference books on saw a with

4、VHDL language preparation intelligent elevator controller program, but is not complete, it gives me the greatest inspiration is signal and inverted algorithm, I discovered this way, then my workload is greatly reduced.I was not only use signal and inverted algorithm outside, still adopted its to the

5、 floor for elevator status transfer basis thought, it is really a good method, but I havent made any progress, one is it is with VHDL language preparation, and Im not very familiar with the language so not particularly understanding. KEY WORDS： A signal and buy verilog CONTENTSChapter I SUMMARY41.1

6、Introduction And Features of FPGA41.2 VHDL Language And Procedures Outlined51.2.1 VHDL Language Development.51.2.2 VHDL Language Features6Chapter II ANALYSIS OF THE ELEVATOR CONTROL SYSTEM .72.1 Background Elevator Control72.2 Specific Purpose And Design Of The Elevator Control Requirements72.3 Elev

7、ator Controller Design Principles And Ideas82.4 Elevator Control System State Diagram Analysis10Chapter III DESIGN AND IMPLEMENTATION OF THE ELEVATOR CONTROL SYSTEM 133.1 VHDL Language Design And Simulation133.1.1 Schematic Description Of Input And Output Modules133.1.2 Module Design Process163.1.3

8、Waveform Simulation183.2 Experimental Platform Elevator Control System To Achieve24Chapter IV SCALABLE DESIGN.25END .27Chapter I SUMMARY1.1 Introduction And Features Of FPGABackgroundCurrently circuit hardware description language (Verilog or VHDL) completed, can be subjected to a simple synthesis a

9、nd layout, fast burn to theFPGAfor testing, the technology mainstream of modernICdesign verification.These elements can be edited can be used to implement some basic logic gates (such asAND, OR, XOR, NOT) or more complex combinational functions such as decoders or mathematical equations.In most of t

10、heFPGAinside, these components can be edited in memory also includes elements such as flip-flops (Flip - flop) or other more complete memory blocks.FPGAWorksFPGAlogic cell arrays using theLCA(LogicCellArray)such a concept, including internal configurable logic blockCLB(ConfigurableLogicBlock),output

11、 input moduleIOB(InputOutputBlock)and internal connections(Interconnect)in three parts.The Basic Features Of TheFPGA1)FPGAdesign usingASICcircuits(ApplicationSpecific IntegratedCircuit),users do not need to cast film production, you can get the combination of chips.2)FPGAspecimendo other full-custom

12、 or semi-customASICcircuit.3)FPGAinternal triggers and richI/Opin.4)FPGAcircuitsASICdesign cycle is the shortest, lowest development costs, one of the least risky devices.5) FPGAwith high-speedCHMOStechnology, low power, compatible withCMOS,TTLlevel.It can be said,FPGAchip is small batch systems to

13、improve system integration, one of the best reliability.1.2 VHDL Language And Procedures Outlined VHDLdescription of a digital system is mainly used for the structure, behavior, functions and interfaces.In addition to containing many statements with external hardware features,VHDLlanguage forms and

14、describe the style and syntax is very similar to the general high-level computer language.The program structure is characteristic of aVHDLengineering or design entity known (can be one element, a circuit module or a system) is divided into external (or the visiblepart,andports)and internal (or non-v

15、isible part) both internal functions and algorithms involved entities partially completed.After a design entity to define the external interface, once its internal development is completed, other designs can call this entity directly.This concept is divided into inner and outer parts of the design e

16、ntity is thebasic point ofVHDLsystem design. 1.2.1 VHDL Language DevelopmentIn the development of integrated circuit manufacturing process technology, microelectronics design process has reached the deep submicron era,mainlyin theEDAdesign collaborative design of hardware and software requirements,

17、existing tools to supportSOCdesign still difficult, urgent need to improve design capacity.In the design language, due toVHLandVerilog HDLis the universal language, in the design of large systems, convenient and intuitive enough, so they need further improvement.As technology advances, electronic pr

18、oducts, upgrading each passing day, and master of electronic products developed power source-EDAtechnology, engineering and technical personnel of our country can not shirk its responsibility, because Chinese companies are mostly still in the design stage of the development of primary, The design to

19、ols are used abroad a few years ago the mainstream tools.1.2.2 VHDL Language FeaturesVHDLlanguage can become standardized hardware description language and is widelyavailable,it is itself bound to have a lot of other hardware description languages do not have the advantage.To sumup,VHDLlanguage has

20、the following advantages:(1) VHDLlanguagepowerful,diverse design approach(2) VHDLhardware description language has a powerful ability(3) VHDLlanguage has a strong ability to transplant (4) VHDLdescription language design and devices Unrelated(5) VHDLlanguage program is easy to share and reuse Chapte

21、r II ANALYSIS OF THE ELEVATOR CONTROL SYSTEM2.1 Background Elevator ControlElevator control system is a fairly complex logic control system.System to simultaneously receive signals on hundreds of processing.Because users of the elevator functional requirements continue to increase.Its corresponding

22、control method are constantly changing.With therapid development ofEDAtechnology.FPGA-based computer control has been widely used in various aspects of circuit design and control of the elevator. 2.2 Specific Purpose And Design Of The Elevator Control RequirementsUseFPGAEnded 6th floor elevator cont

23、rol system.You can use a state machine implementation.Indicates the location where the floor elevator requirements and other necessary signal.Simulation results verify its correctness and the development board hardware testing.Requirements of the system are as follows:1. Elevator six layers.Lift ope

24、rating rules: When rising: a higher position than the current response upstairs requirements, from bottom to top by one execution; if the floor has a downstairs request, thus the request directly to rise tothe top andthenfall into the pattern.After entering the fall mode, only lower than the current

25、 position in response to the request down, from top to bottom by one execution.Elevator six layers up or downalevel every1sec.2. There are lights indicating the state of the elevator is up or down, and there isan elevator to reach thedigitaldisplay layers.3. Each layer has a signal indicating the st

26、ate of the layer of the elevator door, there are two buttons to increase or decrease, respectively, in response to the request4. Each layer inside the elevator reaches the floor of a passenger stop request switches and displays5. After the elevator to stop request has elevator doors open, lights on,

27、4seconds after the elevator doors closed, lights off, until the implementation of End.Finally, a request to issue a final stop at the floor.6. The initial position of the elevator for one layer, in the open state.2.3 Elevator Controller Design Principles and IdeasPrinciple and System Design1,except

28、that the top and bottom, each of the upper and lower floors are provided with request switch, the top and bottom, respectively, fall and rise with the switching request, it should be easy tounderstand;equipped with elevator passengers to request to switch levels.2,lift up or down one level every1s3,

29、after the elevator reaches the floor there is a request stop, after1safter the elevator doors opened, the door lights, lights off after the elevator door5s,elevator continues to run until the end of the last run after the request is docked in the current layer.These are the basic features we should

30、implement.I also mentioned in the preface, finite state machine to achieve real-time control of the elevator is the best way, and by my analysis and related reference library of books, ultimately, referring to some online programs and, finally, the normal operation of the elevator in seven states: u

31、p, down, up process stops midway, down process stops midway, open, close, wait state.Elevator transferred between these seven states is achieved by three-state machine, the transfer of operating an elevator in life generally consistent among the states with the following basicprinciples:1),the direc

32、tion is first priority criterion, which is the teacher who gave us the technical indicators.When the elevator responds to the request with the first running direction, the same direction only when the request after the response, the response to the request to turn in different directions.2),the init

33、ialization state is waiting forafloor door is closed.This would not explain it.In addition to the above analysis I made of the laws governing the operation of the elevator, I choose another reason for the development of intelligent elevator controller is that I want to exercise your own logical thin

34、king and ability to analyze complex problems. 2.4 Elevator Control System State Diagram AnalysisInitially resource I can offer based onDE2board, set the number of floors 6 floors.From my inspection of the books I have summed up the two points that I can learn from.First of all, how to deal with the

35、vast amount of lift of the input signal, if the use of the discussion, the program all the way finished, the complexity is certainly unthinkable, but I still can not guarantee that all of the circumstances analysis to the.always (call_up_1 or call_up_2 or call_up_3 or call_up_4 or call_up_5)up_all =

36、 1b0, call_up_5, call_up_4, call_up_3, call_up_2, call_up_1;/ /The request signals in real-time each fall merger(1stfloor of the ground floor, no decline the request, taking into account the versatility, the first one zero fill)always (call_down_2 or call_down_3 or call_down_4 or call_down_5 or call

37、_down_6)down_all = call_down_6, call_down_5, call_down_4, call_down_3, call_down_2, 1b0;/ /Each stop request signal in real-time consolidationalways (request_1 or request_2 or request_3 or request_4 or request_5 or request_6)request_all = request_6, request_5, request_4, request_3, request_2, reques

38、t_1;This is the signal over a program I used to deal with many kind of juxtaposition of the input signal effective method.Secondly, I learned from the data is how to approach the signal juxtaposed and finite state machines linked.This is evident from the following parameter definitions can get a gli

39、mpse or two.parameter WAIT = 7b0000001, UP = 7b0000010, DOWN = 7b0000100, UPSTOP = 7b0001000, DOWNSTOP = 7b0010000, OPENDOOR = 7b0100000, CLOSEDOOR = 7b1000000;/ /Define symbolic constants floorparameterFLOOR1 = 6b000001, FLOOR2 = 6b000010, FLOOR3 = 6b000100, FLOOR4 = 6b001000, FLOOR5 = 6b010000, FL

40、OOR6 = 6b100000;parameter TRUE = 1b1, FALSE = 1b0 ;/ /define the door open and the door closed symbolic constantsparameter OPEN = 1b1, CLOSED = 1b0 ;/ /define the elevator up, down and still symbolic constantsparameter UPFLAG = 2b01, DNFLAG = 2b10, STATIC = 2b00;Seven states used here implements a f

41、inite state machine.WAITUPUPSTOPDOWNOPENDOORDOWNSTOPCLOSEDOORThe above is my analysis of the two basic lift state transition diagram:Black line:WAIT TO UP TO UPSTOP TO OPENDOOR TO CLOSEDOOR TO WAITPink line:WAIT TO DOWN TO DOWNSTOP TO OPENDOOR TO CLOSEDOOR TO WAITAs the state transitions of the inpu

42、t conditions too much, and I do not draw the reader can own program (with detailed notes) in the grasp.My program uses a standardMEALYtype state machine.Chapter III DESIGN AND IMPLEMENTATION OF THE ELEVATOR CONTROL SYSTEM3.1 VHDL Language Design And Simulation 3.1.1 Schematic Description Of Input An

43、d Output Modules（1） Elevator main controller module :elevator_controller：Port statement：Input Port:call_up_1, call_up_2, call_up_3, call_up_4, call_up_5 were1-5floor uplink request signal,call_down_2, call_down_3, call_down_4, call_down_5, call_down_6 were 2-6 down-request signal buildingrequest_1,

44、request_2, request_3, request_4, request_5, request_6 respectively 1-6 floor inside the elevator dock requestWhen there is a request the respective ports are input is highand low otherwise;respectively, the state transition clock clk,resetthe reset signalOutput Port:PosOutoutput current floor where

45、the elevator,DoorFlagto door signs,UpDnFlagelevator down flagLiftStateoutput current state of the elevator.PosOutvalue for6b000001, 6b000010, 6b000100, 6001000, 6b010000, 6b100000represent elevator in1,2,3,4,5,6floor.Such code words, the comparison judgment in favor of the back.DoorFlagvalue for1b0,

46、 1b1,representing the current door is closed and the current door is open.UpDnFlagvalue for2b00, 2b01, 2b10,representing the current elevator is rising, falling and stationary.LiftState7b0000001, 7b0000010, 7b0000100, 7b0001000, 7b0010000, 7b0100000, 7b1000000,Each elevator is in standby mode, up mo

47、de, down mode, rising to stop, drop stop,sevenstates,such as opening andclosing.（2）Frequency module:frequence_div：Port statement：Input ports:cp_50M;output ports:cp_1;（3）Elevator state arbiter :arbitrator：Port statement：Input ports:elevator_state;count_in;output ports:output open_enable,stop_enable,u

48、p_enable,down_enable,close_enable;（4）LCD driver module:DE2_Default：Port statement：Input ports:input open_enable,stop_enable,up_enable,down_enable,close_enable;inputCLOCK_50;/50 MHzinput KEY;output ports:inout7:0LCD_DATA;/LCD Data bus 8 bitsoutputLCD_ON;/LCD Power ON/OFFoutputLCD_BLON;/LCD Back Light

49、 ON/OFFoutputLCD_RW;/LCD Read/Write Select, 0 = Write, 1 = ReadoutputLCD_EN;/LCD EnableoutputLCD_RS;/LCD Command/DataSelect, 0= Command, 1 = Data3.1.2 Module Design ProcessNow I briefly explain the design process of my module:(1)elevator_controller:This paragraph intelligent elevator controller cons

50、ists of three major components.(A) signal and set part of the completion of the 5-way up the request, the 5-way down the request, the request signal path inside thesixjuxtaposition to simplify.(B) three-part finite state machine.In case there is a request, elevator controller but also according to t

51、he current state of the elevator and the current floor next to the elevator to judge how it works.(C) counter section.Completion of the elevator door closed and time management.(2) frequence_div:This divider50Mhzofacomplete divide operation.Half of the flip traditional counting techniques.(3) arbitr

52、ator:Signal conversion completion signal to the elevator control LCD.Which also uses the elevator main controller in the signal juxtaposed ideas.This can be seen very clearly in my program, I will not repeat them here.(4)DE2_Default:This module I was a used.DE2board because it is provided by the sou

53、rce, so it is still relatively easy to prepare.It just added aproducedifferent output depending on the input module.Midway also encountered the problem of character LCD can not be updated, but with the help of students, the ultimately resolved.(5)digital decoder module:(6)digital time decoding modul

54、e:These two modules together to talk more appropriate, because they are using the same coding principles, but just not the same conditions.We can target different input according to their own wishes to translate it into the same digital display.3.1.3 Waveform simulation（1）When the elevator is in the

55、 initial state, the elevator down at the top there is a request：（2）LCD display because the data too, so alone shown below：First Show：“ it is static. ”Then displays：After more characters sent to the LCD module can display “ door is rising. ”Then displays：Then displays “ it is static. ”After more char

56、acters sent to the LCD module can display “ door is opening. ”Then displays：After more characters sent to the LCD module can display “ it is closing. ”Finally, the following characters will be displayed, lift back to the initial waiting state：The above can be displayed “ it is static. ” Note: Due to

57、 the LCD display waveform will occupy more space, so Im only in high-rise above downward request as an example to illustrate the state of the elevator through the LCD can be displayed properly. In view of this, I will not be below shows the waveform of a waveform diagram of the LCD display portion（3

58、）When the elevator stopped at the sixth floor in a wait state, on the first floor and the second floor there are upwards of requests simultaneously：（4）When the elevator stopped at a floor in a wait state, in the 6th and 5th floor down requests simultaneously：（5）When the elevator stopped at the sixth

59、 floor, there is a request in the 5th floor down, the elevator should be first on the fifth floor, inside the elevator to a floor request, if the elevator on the way down, there is a request on the second floor when upward elevator should first request the appropriate internal and external requests

60、accordingly：（6）Forced to run the elevator button forbid：3.2 Experimental Platform Elevator Control System To Achieve Chapter IV SCALABLE DESIGNIn this design, considering the scalability, so the signal is defined when using the binary vector, rather than integers.In the design approach also made a s

61、pecial design, it makes better scalability.If you want to achieven-story elevator control, first at the local port must join all the buttons, and lights as long as the vectorn 6can be changed.Also need to add other key indicators trigger buttons control the process in the statement.In the down state

62、 of the elevator6into n, in the open state into the elevator 2 n-1, in the closing state, theposition = 6intoposition =n, the key is to modify theposition =section 6, according to the each list will be very cumbersome, so you have to look for commonalities layers judgment conditions, one solution is that a new global vectorabcisstd_logic_vector (n downto 1), abcassignment asabc 1 , other =0).When the elevator rises mode, if there is this layer request signal, the elevator door; If