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1、116 BIT KOGGE-STONE TREE ADDERhttp:/ Abstract Introduction Why Tree Adder?Theory Project Details Summary of Results Lessons Learned Cost Analysis Conclusionhttp:/ We designed 16 bit Kogge-Stone Tree Adder-the most commonly used parallel prefix carry-lookahead adder topology.200MHz clock frequency Ar
2、ea 1000*600 um2 Power density AMI06 Technologyhttp:/ Why?-minimum logic depth,wide wiring channels,regular structure and large fanout points.Prefix Adder StructureS1B1A1P1G1G0:0S2B2P2G2G1:0A2S3B3A3P3G3G2:0S4B4P4G4G3:0A4CinG0P01:Bitwise PG logic2:Group PG logic3:Sum logicC0C1C2C3CoutC4http:/ DETAILS1
3、7 pin outs 33 input D-flip flops and 17 output D-flip flopsCreate schematic and layout for 16 bit tree adderTest schematic using test benchRun DRC and LVS to verify the designhttp:/ BLOCK DIAGRAM1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:143:04:15:26:37:48:59:610:711:812:913:1014:1115:124
4、:05:06:07:08:19:210:311:412:513:614:715:82:0012345678910111213141515:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0http:/ path calculationTphl=5ns/(14+3)=.29nshttp:/ of actual Wn&Wphttp:/ Reporthttp:/ reporthttp:/ Reporthttp:/ Analysis Estimate amount of time spent on project:-Verifyi
5、ng NC Verilog5 hrs-Verifying Timing10 hrs-Layout40 hrs-Post Extracted Timing10 hrshttp:/ Learned Start early Work in group Study previous projects Seek advice from Dr.Parent and previous students Save time for debugging error http:/ We designed and implemented a 16 bit Kogge-Stone Tree Adder that operates at 200MHz in an area of 1000*600 um2http:/ Thanks to Cadence Design Systems for the VLSI lab Thanks to Dr.David Parent Thanks to all 166,167,and 224 studentshttp:/
BIT KOGGESTONE TREE ADDER语文
