可编程逻辑器件与硬件描述语言实验报告

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1、可编程逻辑器件与硬件描述语言实 验 报 告评 语：成绩 教 师： 年 月 日 分 组：第（ ）组班 级： 学 号： 姓 名： 地 点： 时 间： 实验一：3-8译码器设计实验目的：1）掌握ISE开发工具的使用，掌握FPGA开发的基本步骤；2）掌握组合逻辑电路设计的一般方法；3）掌握程序下载方法，了解UCF文件的格式；4）初步了解开发板资源，掌握开发板使用方法。重点了解滑动开关和LED显示灯的使用方法。实验内容：用VHDL实现3-8译码器模块将程序下载到FPGA并进行检验实验步骤：1）启动ISE，新建工程文件，编写3-8译码器的VHDL模块；2）新建UCF文件，输入位置约束；3）完成综合、实现，

2、生成下载文件；4）连接开发板USB下载线，开启开发板电源；5）下载到FPGA；6）拨动开关，验证结果是否正确。实验代码： - Company: - Engineer: - - Create Date: 19:03:03 10/01/2011 - Design Name: - Module Name: decoder38 - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created-

3、Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-libr

4、ary UNISIM;-use UNISIM.VComponents.all;entity decoder38 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; EN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (7 downto 0);end decoder38;architecture Behavioral of decoder38 issignal din: std_logic_vector(2 downto 0);begindin = A&B&C;PROCESS(din,

5、EN)beginif (EN=1) THENY y y y y y y y y y=00000000;end case;end if;end process;end Behavioral;1.2、UCF文件：NET y LOC = F9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = D11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y

6、LOC = C11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = F11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E12 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = F12 | IOSTANDARD = LVTTL | SLEW = SLOW

7、 | DRIVE = 8 ;NET EN LOC = L13 | IOSTANDARD = LVTTL | PULLUP ;NET C LOC = L14 | IOSTANDARD = LVTTL | PULLUP ;NET B LOC = H18 | IOSTANDARD = LVTTL | PULLUP ;NET A LOC = N17 | IOSTANDARD = LVTTL | PULLUP ;实验结果：用滑动开关SW3SW1作为输入A，B，C；滑动开关SW0控制EN；8个LED灯表示8个输出。当SW0处于ON（EN=1）位置时，所有LED灯灭；当SW0处于OFF（EN=0），反映当前

8、输入的译码输出在LED灯上显示，即当输入为000（滑动开关SW3-SW1处于OFF状态），LED0亮，其它灯灭，等等实验二：可逆计数器设计实验目的：1）进一步熟练ISE开发工具，巩固FPGA开发的基本步骤，掌握功能仿真方法；2）掌握时序逻辑电路设计的一般方法，掌握时钟分频程序设计方法；3）理解VHDL的层次结构设计；4）巩固程序下载方法；5）了解开发板时钟资源，以及时钟分频方法。实验内容：实现如下可逆计数器表3-1 可逆计数器功能表clrenUp/Dnclk Y7 Y01XXX0000000000XX停止计数011计数器+1操作010计数器-1操作实现如下基本的可逆计数器资源使用要求及实现方法

9、：1）用LED0LED7作为计数器输出显示，LED7为高位，LED0为低位；2）SW0为计数方向up/dn控制；3）SW1为计数允许EN控制端；4）BTN_EAST为clr按钮；5）计数时钟频率为1Hz，通过对50Mhz系统时钟分频得到，分频电路独立编写一个模块，如图3-2所示；6）扩展：可以对按键次数进行计数（按键为BTN_SOUTH），即通过SW2选择计数源。二选一电路如图3-3所示。7）将图3-1图3-3三个模块连接起来，构成一个完整计数器。如图3-4所示电路图1/500000050M clock1Hz clock图3-2 1/5000000分频器2选1In1Dout图3-3 二选一电路

10、In2SEn(SW1)clkY0（LED0）Y3（LED3）Y4（LED4）Y5（LED5）Y6（LED6）Y7（LED7）Up/Dn(SW0)2选1SW2clr(BTN_EAST)BTN_SOUTH1/5000000图3-4 完整的可逆计数器实验代码：计数器代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.STD_LOGIC_ARITH.ALL;entity countercore is Port ( clr : in STD_LOGIC; en : in STD_LOGIC

11、; dir : in STD_LOGIC; clk : in STD_LOGIC; Yout : out STD_LOGIC_VECTOR (7 downto 0);end countercore;architecture Behavioral of countercore issignal result:std_logic_vector(7 downto 0) := 00000000;beginprocess(clr)beginif (clr = 1) thenresult = 00000000;elsif (en = 1) thenif (clkevent and clk = 1) the

12、nif (dir = 1) thenresult = result + 1;elseresult = result -1;end if;end if;end if;end process;Yout = result;end Behavioral;时钟分频器代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity freqdiv is Port ( clkin : in STD_LOGIC; clkout : out STD_LOGIC);end freqdiv;architecture Behavioral of freqdiv isbeginproc

13、ess(clkin)variable cnt:integer := 0;beginif (clkinevent and clkin = 1) thencnt := cnt + 1;if (cnt = 25000000) thenclkout = 0;elsif (cnt = 50000000) then -50000000cnt := 0;elseclkout = 1;end if;end if;end process;end Behavioral;2选1选择器代码entity mux21 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : in

14、 STD_LOGIC; dout : out STD_LOGIC);end mux21;architecture Behavioral of mux21 isbeginprocess(a,b,s)beginif (s = 0) thendout = a;elsedout = b;end if;end process;end Behavioral;UCF代码NET y LOC = F9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE

15、= 8 ;NET y LOC = D11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = C11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = F11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET y LOC = E12 | IOSTANDARD = LVTTL |

16、SLEW = SLOW | DRIVE = 8 ;NET y LOC = F12 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;# PlanAhead Generated physical constraints NET btn_in LOC = K17 | IOSTANDARD = LVTTL | PULLDOWN;NET clk LOC = C9 | IOSTANDARD = LVCMOS33 ;NET clr LOC = H13 | IOSTANDARD = LVTTL | PULLDOWN ;NET dir LOC = L13 | IO

17、STANDARD = LVTTL | PULLUP ;NET en LOC = L14 | IOSTANDARD = LVTTL | PULLUP ;NET sw_in LOC = H18 | IOSTANDARD = LVTTL | PULLUP ;实验结果：计数时钟频率为1Hz，通过对50Mhz系统时钟分频得到，分频电路独立编写一个模块，并对按键次数进行计数实验三：按键抖动消除及验证电路设计实验目的：1）进一步熟练ISE开发工具，巩固FPGA开发的基本步骤，掌握功能仿真方法；2）了解按键抖动的原因，抖动消除方法3）掌握状态机的设计方法；4）掌握消除抖动的状态机设计方法5）巩固程序下载方法；

18、。实验内容：原理简介按键动作发生时,按键的输出会出现不稳定的逻辑0和逻辑1的跳变。该信号直接输入到计数器之类电路,会发生计数错误。如图3-5所示。图3-5 信号抖动提示：状态机设计思路设置十个状态：S0，S1，S2，S3，S4，S5。电路的复位信号RST有效时，电路进入复位状态S0，在S0状态下，时钟信号CLK以一定频率采样按键输入信号Key_in，如果采样到Key_in = 0，则停留在S0状态，并继续采样，一旦采样到Key_in=1，则转入S1延时状态，进行消抖延时，当延时结束时，Delay_end=1，则转入S2状态，在此状态下，时钟信号CLK以一定频率采样按键输入Key_in，如果Ke

19、y_in = 0则转入S0，否则转入S3；状态S3，S4的转换过程和条件与S2相同，在状态S4下，如果Key_in=1，则转入S5状态，当进入S5时，表示经过S2，S3，S4三个连续状态检测按键输入Key_in都为1，则认为按键处于稳定状态，在S5输出按键确认信号Key_confirm=1。同时在状态S5下，时钟信号CLK检测按键输入Key_in，如果Key_in = 1，表示按键未释放，继续停留在S5，检测输入信号，如果检测到Key_in = 1，表示按键已经释放，输出Key_confirm = 0, 返回到状态S0，等待下一次按键操作。 资源使用要求：用LED0LED7作为计数输出；BTN

20、_EAST作为按键。实验步骤：1）画出电路的状态转换图；2）编写完整的VHDL程序；3）下载程序，进行验证实验代码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mystate is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; key_in : in STD_LOGIC; key_confirm : out STD_LOGIC:=0);end mystate;architecture Behavioral of mystate is

21、 TYPE STATE_TYPE IS(s0,s1,s2,s3,s4,s5); SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;begin process(current_state,key_in) begin case current_state is when s0= if(key_in=0)thennext_state=s0;elsenext_state if(key_in=0)thennext_state=s0;elsenext_state if(key_in=0)thennext_state=s0;elsenext_state if(key_in

22、=0)thennext_state=s0;elsenext_state if(key_in=0)thennext_state=s0;elsenext_state key_confirm=1;if(key_in=0)thennext_state=s0;elsenext_state=s5;end if;end case;end process;process(clk,rst) begin if(rst=1)then current_state=s0; elsif(clkevent and clk=1)then current_staterst := rst + 1;if(rst = 100)the

23、nif(a= 1) then Current_state = s1;count =0;rst := 0;elsif(b=1) thenCurrent_state = s2;count count =count+1;if(b = 1)thenCurrent_state = s0;count = 1000;elsif(count = 100)thenCurrent_state count =count - 1;if(a = 1)thenCurrent_state = s0;count = 1000;elsif(count = 699)thenCurrent_state count =count+1

24、;if(b = 1)thenCurrent_state = s0;count = 500)thenCurrent_state count =count-1;if(a = 1)thenCurrent_state = s0;count = 1000;elsif(count = 399)thenCurrent_state count =count+1;if(b = 1)thenCurrent_state = 800)thenCurrent_state = s0;count count =count-1;if(a = 1)thenCurrent_state = s3;elsif(count = 0)t

25、henCurrent_state = s0;count = 1000;end if;end case;end if;end process statefsm;Yout:process(sig,count)beginif(rising_edge(sig)thenY=t;if(count = 800)thent 0 and count 100)thent= 10011000;elsif(count 200)thent= 01011000;elsif(count 300)thent= 00111000;elsif(count 500)thent= 00011000;elsif(count 600)t

26、hent= 00011100;elsif(count 700)thent= 00011010;elsif(count 800)thent= 00011001;end if;end if;end process Yout;end Behavioral;- Company: - Engineer: - - Create Date: 23:54:10 11/09/2011 - Design Name: - Module Name: fenpinqi - Behavioral - Project Name: - Target Devices: - Tool versions: - Descriptio

27、n: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declara

28、tion if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity fenpinqi is Port ( a : in STD_LOGIC; b : out STD_LOGIC);end fenpinqi;architecture Behavioral of fenpinqi isbeginprocess(a)variable cout:integer :=1;beginif rising_edge(a) thencout:=cout+1;if(

29、cout=250000) then b=0;elsif(cout500000) then bif(a= 1) then Current_state = s1;elsenull;end if;b count :=count-1;if(count =0) thenCurrent_state if(a= 0) then Current_state = s0;elseCurrent_state if(a= 0) then Current_state = s0;elseCurrent_state if(a= 0) then Current_state = s0;elseCurrent_state if(

30、a= 0 ) then Current_state = s0;elsenull;end if;b = 1;end case;end if;end process statefsm;end Behavioral;NET SW3 LOC = N17 | IOSTANDARD = LVTTL | PULLUP ;NET BTN_EAST LOC = H13 | IOSTANDARD = LVTTL | PULLDOWN ;NET LED LOC = F9 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = E9 | IOSTAN

31、DARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = D11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = C11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = F11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = E11 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = E12 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET LED LOC = F12 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET clk50 LOC = C9 | IOSTANDARD = LVCMOS33 ;心得体会： 。