最新MSP430G2553学习笔记(数据手册)

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1、精品资料MSP430G2553学习笔记(数据手册).MSP430G2553学习笔记（数据手册）MSP430G2553性能参数(DIP-20)工作电压范围：1.83.6V。5种低功耗模式。16位的RISC结构，62.5ns指令周期。超低功耗：运行模式-230A；待机模式-0.5A；关闭模式-0.1A；可以在不到1s的时间里超快速地从待机模式唤醒。基本时钟模块配置：具有四种校准频率并高达16MHz的内部频率；内部超低功耗LF振荡器；32.768KHz晶体；外部数字时钟源。两个16 位Timer_A，分别具有三个捕获/比较寄存器。用于模拟信号比较功能或者斜率模数(A/D)转换的片载比较器。带内部基准

2、、采样与保持以及自动扫描功能的10位200-ksps 模数(A/D)转换器。16KB闪存，512B的RAM。16个I/O口。 注意：MSP430G2553无P3口！MSP430G2553的时钟基本时钟系统的寄存器DCOCTL-DCO控制寄存器DCOx DCO频率选择控制1MODxDCO频率校正选择，通常令MODx=0 注意：在MSP430G2553上电复位后，默认RSEL=7，DCO=3，通过数据手册查得DCO频率大概在0.81.5MHz之间。BCSCTL1-基本时钟控制寄存器1XT2OFF 不用管，因为MSP430G2553内部没有XT2提供的HF时钟XTS 不用管，默认复位后的0值即可DI

3、VAx设置ACLK的分频数00/101/210/411/8RSELx DCO频率选择控制2BCSCTL2-基本时钟控制寄存器2SELMxMCLK的选择控制位00DCOCLK01DCOCLK10LFXT1CLK或者VLOCLK11LFXT1CLK或者VLOCLKDIVMx设置MCLK的分频数00/101/210/411/8SELS SMCLK的选择控制位 0DCOCLK 1LFXT1CLK或者VLOCLKDIVSx设置SMCLK的分频数00/101/210/411/8DCOR DCO直流发生电阻选择，此位一般设00内部电阻 1外部电阻BCSCTL3-基本时钟控制寄存器3XT2Sx 不用管LFXT

4、1Sx00LFXT1选为32.768KHz晶振01保留10VLOCLK11外部数字时钟源XCAPx LFXT1晶振谐振电容选择001pF016pF1010pF1112.5pFmsp430g2553.h中基本时钟系统的内容/* Basic Clock Module*/#define _MSP430_HAS_BC2_ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System C

5、ontrol 1 */SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0

6、x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL

7、3 (0x08) /* Range Select Bit 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */#define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider

8、1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */#d

9、efine DIVM1 (0x20) /* MCLK Divider 1 */#define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* S

10、MCLK Divider 3: /8 */#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */#define SELM_1 (0x40) /* MCLK Source Se

11、lect 1: DCOCLK */#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/

12、XOUT Cap 0 */#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S0 (0x40) /* Mode 0 for XT2 */#define XT2S1 (0x80) /* Mode 1 for XT2 */#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define

13、 XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LF

14、XT1 : VLO */#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital inpu

15、t signal */基本时钟系统例程(DCO) MSP430G2553在上电之后默认CPU执行程序的时钟MCLK来自于DCO时钟。TI提供的Launch Pad上，P1.0和P1.6分别接了红色和绿色的LED灯，下面写一个程序让它们交替闪烁；之后我们来改变DCO的频率，进而使软延时时间变化，可以看到LED闪烁间隔有变化。#include msp430g2553.hvoid main(void)WDTCTL = WDTPW + WDTHOLD;P1DIR |= BIT0 + BIT6;while(1)P1OUT = BIT0 + BIT6;_delay_cycles(100000);这段程序采

16、用430上电后默认的DCO频率，假设是1MHz的话，则延时100000个DCO提供的MCLK大概是0.1s左右。下面一段程序，将DCOx设置为1，RSELx设置为1，通过数据手册查得DCO频率大概在0.060.14MHz之间，所以明显MCLK要慢得多了，因此LED闪烁时间延长。#include msp430g2553.hvoid main(void)WDTCTL = WDTPW + WDTHOLD;DCOCTL |= DCO0;DCOCTL &=(DCO1 + DCO2);BCSCTL1 |= RSEL0;BCSCTL1 &= (RSEL1 + RSEL2 + RSEL3);P1DIR |=

17、BIT0 + BIT6;while(1)P1OUT = BIT0 + BIT6;_delay_cycles(100000);MSP430G2553的I/O口MSP430G2553共有2组数字I/O口：P1和P2，每组各有8个引脚，每个引脚都能够响应中断，接受外部输入的上升沿或者下降中断请求。所有I/O口均与单片机内部外设的特殊功能引脚复用，当我们选用I/O功能时，要作为通用I/O口来使用，这需要相应的寄存器来进行控制。I/O头文件内容/* DIGITAL I/O Port1/2 Pull up / Pull down Resistors*/#define _MSP430_HAS_PORT1_R

18、_ /* Definition to show that Module is available */#define _MSP430_HAS_PORT2_R_ /* Definition to show that Module is available */SFR_8BIT(P1IN); /* Port 1 Input */SFR_8BIT(P1OUT); /* Port 1 Output */SFR_8BIT(P1DIR); /* Port 1 Direction */SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */SFR_8BIT(P1IES); /

19、* Port 1 Interrupt Edge Select */SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */SFR_8BIT(P1SEL); /* Port 1 Selection */SFR_8BIT(P1SEL2); /* Port 1 Selection 2 */SFR_8BIT(P1REN); /* Port 1 Resistor Enable */SFR_8BIT(P2IN); /* Port 2 Input */SFR_8BIT(P2OUT); /* Port 2 Output */SFR_8BIT(P2DIR); /* Port 2

20、 Direction */SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */SFR_8BIT(P2SEL); /* Port 2 Selection */SFR_8BIT(P2SEL2); /* Port 2 Selection 2 */SFR_8BIT(P2REN); /* Port 2 Resistor Enable */P1口P1.0、P1.1、P1.2P1.3

21、P1.4P1.5、P1.6、P1.7P2.0、P2.1、P2.2、P2.3、P2.4、P2.5P2.6P2.7P1DIR用来选择I/O口是输入还是输出，0为输入，1为输出。P1IN为输入寄存器，外部的电平输入状态可从此寄存器相应的位读取。P1OUT为输出寄存器，向外输出的电平状态可从此寄存器送出。P1SEL和P1SEL2为引脚功能选择。MSP430G2553的Timer_ATimer_A的工作原理MSP430G2553内部有两个Timer_A模块，分别是Timer0_A3和Timer1_A3。“3”表示每个Timer_A模块有3组“捕获/比较”寄存器。Timer_A的主要特性包括：(1) 具有

22、16位定时/计数功能，3种计数模式可选(2) 16位定时计数器时钟源可选(3) 可在CPU不介入的情况下，产生PWM波(4) 计数器溢出可产生中断Timer_A又两部分组成：主计数器和比较捕获模块。其中主计数器如下图。TAR为16主计数器的当前计数值，可对TAR赋初值。主计数器计数时钟有4种来源，通过TASSELx来进行选择。IDx可对输入时钟进行分频，TACLR为主计数器的清零控制位，MCx用来选择主计数器的4种计数模式，TAIFG为主计数器中断标志位。TASSELx：00=外部管脚时钟输入 01=ACLK 10=SMCLK 11=TACLK取反IDx：00=不分频 01=2分频 10=4分

23、频 11=8分频TACLR：0=不清零 1=清零Timer_A一共有三种计数模式，分别是：增计数、连续增计数和增减计数。增计数模式下，每个时钟周期计数值TAR加1，当TAR值超过TACCR0时，TAR自动清零，并且置位TAIFG标志位。而后TAR从0值重新开始加1。改变TACCR0的值即可改变定时周期。连续增计数模式下，TAR从零加1，加到溢出值0xFFFF为止，之后自动归零重新开始。通常我们利用该计数模式进行信号的捕捉，利用TACCRx寄存器存储捕获发生的时刻。增减计数模式下，TAR的值从零加到TACRR0，而后再减到零，如此循环。通常我们利用该计数模式产生对称、可加死区延时的PWM波。Ti

24、mer_A的另一重要组成部分，是捕获/比较模块，每个Timer_A均有3个捕获/比较模块，它的作用主要有两方面。一是在比较模式下，每个捕获/比较模块都拿自身捕获/比较寄存器TACCRx的值与主计数器TAR的值比较，一旦相等，就自动的改变某个引脚的输出电平，一共有8种电平变化规律可选，这样可以在无CPU干预的情况下产生PWM波；二是在捕获模式下，从某个指定引脚的输入电平跳变可以触发捕获电路，并将此时主计数器的数值自动保存到相应的捕获值寄存器TACCRx中，这个过程纯硬件实现，无CPU干预，可以用来测量频率、占空比等。捕获/比较模块结构图如下：CAP用来切换选择捕获/比较工作模式；CCISx选择捕

25、获输入源；CMx选择捕获触发沿状态，COV为捕获溢出标志位，如果前一次的捕获值未被读取而新的捕获已经产生，则溢出标志位会置位；捕获引脚的电平状态可以实时的通过CCI读出；由于捕获信号可能与时钟信号不同步，从而产生数字电路竞争，我们可以置位SCS进行同步捕获，假设实际信号的发生时刻值为N，那么同步捕捉到的值将为N+1，建议均采用同步捕捉。在比较模式下，我们可以通过程序填写TACCRx的值，硬件会自动的将该值与TAR的值进行比较，一旦相等，即产生EQU信号，则通过输出引脚产生电平变化，其中OUTMODEx可以选择电平变化的8种方式，这样就可以产生不同种类的PWM波。OUT可以控制引脚的输出电平(高

26、、低的选择)。已Timer0_A3为例，其捕获/比较引脚均与I/O口复用，具体复用引脚参加数据手册。在比较输出模式0下，输出引脚的状态由OUT位控制。其余7种模式下，引脚电平的变化如下图：增计数模式下连续增计数模式下增减计数模式下Timer_A头文件内容/* Timer0_A3*/#define _MSP430_HAS_TA3_ /* Definition to show that Module is available */SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */SFR_16BIT(TA0CTL); /* Timer0_A

27、3 Control */SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */SFR_16BIT(TA0R); /* Timer0_A3 */SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */SFR_16BIT(TA0CCR1

28、); /* Timer0_A3 Capture/Compare 1 */SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */* Alternate register names */#define TAIV TA0IV /* Timer A Interrupt Vector Word */#define TACTL TA0CTL /* Timer A Control */#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */#define TACCTL1 TA0CCT

29、L1 /* Timer A Capture/Compare Control 1 */#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */#define TAR TA0R /* Timer A */#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */#d

30、efine TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */#define TACTL_ TA0CTL_ /* Timer A Control */#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */#def

31、ine TAR_ TA0R_ /* Timer A */#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */* Alternate register names 2 */#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define CCTL

32、1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Ca

33、pture/Compare Control 0 */#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define CCR2_ TACCR2_ /* Timer A Capture/C

34、ompare 2 */#define TASSEL1 (0x0200) /* Timer A clock source select 1 */#define TASSEL0 (0x0100) /* Timer A clock source select 0 */#define ID1 (0x0080) /* Timer A clock input divider 1 */#define ID0 (0x0040) /* Timer A clock input divider 0 */#define MC1 (0x0020) /* Timer A mode control 1 */#define

35、MC0 (0x0010) /* Timer A mode control 0 */#define TACLR (0x0004) /* Timer A counter clear */#define TAIE (0x0002) /* Timer A counter interrupt enable */#define TAIFG (0x0001) /* Timer A counter interrupt flag */#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */#define MC_1 (1*0x10u) /* Timer

36、 A mode control: 1 - Up to CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */#define ID_2 (2*0x40u

37、) /* Timer A input divider: 2 - /4 */#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2

38、- SMCLK */#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000) /* Capture mode 1 */#define CM0 (0x4000) /* Capture mode 0 */#define CCIS1 (0x2000) /* Capture input select 1 */#define CCIS0 (0x1000) /* Capture input select 0 */#define SCS (0x0800) /* Capture sy

39、chronize */#define SCCI (0x0400) /* Latched capture signal (read) */#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080) /* Output mode 2 */#define OUTMOD1 (0x0040) /* Output mode 1 */#define OUTMOD0 (0x0020) /* Output mode 0 */#define CCIE (0x0010) /* Capture/compare

40、 interrupt enable */#define CCI (0x0008) /* Capture input signal (read) */#define OUT (0x0004) /* PWM Output signal if output mode 0 */#define COV (0x0002) /* Capture/compare overflow flag */#define CCIFG (0x0001) /* Capture/compare interrupt flag */#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 -

41、 output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */#define OUTMOD_5 (5*0x20u) /* P

42、WM output mode: 5 - Reset */#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */#define C

43、CIS_2 (2*0x1000u) /* Capture input select: 2 - GND */#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */#define CM_3

44、 (3*0x4000u) /* Capture mode: 1 - both edges */* T0_A3IV Definitions */#define TA0IV_NONE (0x0000) /* No Interrupt pending */#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */#define TA0IV_6 (0x0006) /* Reserved */#define TA0IV_8 (0x0008) /* Reserved *

45、/#define TA0IV_TAIFG (0x000A) /* TA0IFG */* Timer1_A3*/#define _MSP430_HAS_T1A3_ /* Definition to show that Module is available */SFR_16BIT(TA1IV); /* Timer1_A3 Interrupt Vector Word */SFR_16BIT(TA1CTL); /* Timer1_A3 Control */SFR_16BIT(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */SFR_16BIT(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1