静态时序分析基本原理和时序分析模型课件

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1、 2009 Altera Corporation1Quartus II Software Design Series: Timing Analysis- Timing analysis basics 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation2ObjectivesnDisplay a complete understanding of timing analysis 2

2、009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation3How does timing verification work?nEvery device path in design must be analyzed with respect to timing specifications/requirements-Catch timing-related errors faster

3、 and easier than gate-level simulation & board testingnDesigner must enter timing requirements & exceptions-Used to guide fitter during placement & routing-Used to compare against actual results INCLKOUTDQCLRPREDQCLRPREcombinational delaysCLR 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, M

4、AX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation4Timing Analysis BasicsnLaunch vs. latch edgesnSetup & hold timesnData & clock arrival timenData required timenSetup & hold slack analysisnI/O analysisnRecovery & removalnTiming models 2009 Altera CorporationAltera, Strati

5、x, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation5Path & Analysis TypesThree types of Paths:Clock PathsData Path1.Asynchronous Paths*Clock PathsAsync PathData PathAsync PathDQCLRPREDQCLRPRETwo types of Analysis:Synchronous clock & data paths1.Asynchro

6、nous* clock & async paths*Asynchronous refers to signals feeding the asynchronous control ports of the registers 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation6Launch & Latch EdgesCLKData ValidDATALaunch Edge:th

7、e edge which “launches” the data from source registerLatch Edge:the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle) 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCo

8、re are trademarks of Altera Corporation7Setup & HoldSetup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock edgeDQCLRPRECLKThValidDATATsuCLKDATATogether, the setup time and hold time form a Data Required Window, the time around a

9、clock edge in which data must be stable. 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation8Data Arrival TimeData Arrival Time = launch edge + Tclk1 + Tco +TdataCLKREG1.CLKTclk1Data ValidREG2.DTdataLaunch EdgeData V

10、alidREG1.QTconThe time for data to arrive at destination registers D inputREG1PRED QCLRREG2PRED QCLRTclk1TCOTdata 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation9Clock Arrival TimeClock Arrival Time = latch edge

11、+ Tclk2 CLKREG2.CLKTclk2Latch EdgenThe time for clock to arrive at destination registers clock inputREG1PRED QCLRREG2PRED QCLRTclk2 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation10Data Required Time - SetupData

12、Required Time = Clock Arrival Time - Tsu - Setup Uncertainty CLKREG2.CLKTclk2Latch EdgenThe minimum time required for the data to get latched into the destination registerTsuData ValidREG2.DData must be valid hereREG1PRED QCLRREG2PRED QCLRTclk2Tsu 2009 Altera CorporationAltera, Stratix, Arria, Cyclo

13、ne, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation11Data Required Time - HoldData Required Time = Clock Arrival Time + Th + Hold Uncertainty CLKREG2.CLKTclk2Latch EdgenThe minimum time required for the data to get latched into the destination registerThData mustremai

14、n validto hereData ValidREG2.DREG1PRED QCLRREG2PRED QCLRTclk2Th 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation12Tclk2Setup SlackREG2.CLKnThe margin by which the setup timing requirement is met. It ensures launch

15、ed data arrives in time to meet the latching requirement.TsuCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTco Setup SlackLaunch EdgeLatch EdgeREG1PRED QCLRREG2PRED QCLRTclk1TCOTdataTclk2Tsu 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are

16、trademarks of Altera Corporation13Setup Slack (contd)Positive slack-Timing requirement metNegative slack-Timing requirement not met Setup Slack = Data Required Time Data Arrival Time 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of

17、Altera Corporation14Hold SlackREG2.CLKTclk2nThe margin by which the hold timing requirement is met. It ensures latch data is not corrupted by data from another launch edge. ThCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTcoHoldSlackLatch EdgeNext Launch EdgeREG1PRED QCLRREG2PRED QCLRTclk1TCO

18、TdataTclk2Th 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation15Hold Slack (contd)Positive slack-Timing requirement metNegative slack-Timing requirement not met Hold Slack = Data Arrival Time Data Required Time 200

19、9 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation16FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O Analysis nAnalyzing I/O performance in a synchronous design uses the same slack equations-Must include external device & PCB tim

20、ing parametersreg1PRED QCLRreg2PRED QCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCData Arrival PathData Arrival PathData Required Path* Represents delay due to capacitive loading 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporati

21、on17Recovery & RemovalRecovery:The minimum time an asynchronous signal mustbe stable BEFORE clock edgeRemoval:The minimum time an asynchronous signal mustbe stable AFTER clock edgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quart

22、us, and MegaCore are trademarks of Altera Corporation18Asynchronous = Synchronous?nAsynchronous control signal source is assumed synchronous-Slack equations still applyldata arrival path = asynchronous control pathlTsu Trec; Th Trem-External device & board timing parameters may be needed (Ex. 1)ASSP

23、reg1PRED QCLRFPGA/CPLDreg2PRED QCLROSCFPGA/CPLDreg1PRED QCLRreg2PRED QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required path 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation19W

24、hy Are These Calculations Important?nCalculations are important when timing violations occur-Need to be able to understand cause of violationnExample causes-Data path too long-Requirement too short (incorrect analysis) -Large clock skew signifying a gated clock, etc.nTimeQuest timing analyzer uses t

25、hem-Equations to calculate slack-Terminology (launch and latch edges, Data Arrival Path, Data Required Path, etc.) in timing reports 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation20Timing Models in DetailnQuartu

26、s II software models device timing at two PVT conditions by default-Slow Corner ModellIndicates slowest possible performance for any single pathlTiming for slowest device at maximum operating temperature and VCCMIN-Fast Corner ModellIndicates fastest possible performance for any single pathlTiming f

27、or fastest device at minimum operating temperature and VCCMAXnWhy two corner timing models?-Ensure setup timing is met in slow model-Ensure hold timing is met in fast modellEssential for source synchronous interfacesnThird model (slow, min. temp.) available only for 65 nm and smaller technology devi

28、ces (temperature inversion phenomenon) 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation21Generating Fast/Slow NetlistnSpecify one of the default timing models to be used when creating your netlistnDefault is the s

29、low timing netlistnTo specify fast timing netlist-Use -fast_model option with create_timing_netlist command-Choose Fast corner in GUI when executing Create Timing Netlist from Netlist menu-CANNOT select fast corner from Tasks Pane 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy

30、, Nios, Quartus, and MegaCore are trademarks of Altera Corporation22Specifying Operating Conditions nPerform timing analysis for different delay models without recreating the existing timing netlistnTakes precedence over already generated netlistnRequired for selecting slow, min. temp. model and oth

31、er models (industrial, military, etc.) depending on devicenUse get_available_operating_conditions to see available conditions for target device 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera CorporationReference DocumentsnQ

32、uartus II Handbook, Volume 3, Chapter 7 The Quartus II TimeQuest Timing AnalyzernQuick Start Tutorial nCookbook 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera CorporationReference DocumentsnSDC and TimeQuest API Reference M

33、anualnAN 481: Applying Multicycle Exceptions in the TimeQuest Timing AnalyzernAN 433: Constraining and Analyzing Source-Synchronous Interfaces 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation25Instructor-Led Train

34、ingWith Alteras instructor-led training courses, you can: Listen to a lecture from an Altera technical training engineer (instructor) Complete hands-on exercises with guidance from an Altera instructor Ask questions & receive real-time answers from an Altera instructor Each instructor-led class is o

35、ne or two days in length (8 working hours per day). Online TrainingWith Alteras online training courses, you can: Take a course at any time that is convenient for youTake a course from the comfort of your home or office (no need to travel as with instructor-led courses) Each online course will take

36、approximate one to three hours to complete. View training class schedule & register for a classLearn More Through Technical Training 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation26Altera Technical SupportnRefer

37、ence Quartus II software on-line help nQuartus II HandbooknConsult Altera applications (factory applications engineers)-MySupport: -Hotline: (800) 800-EPLD (7:00 a.m. - 5:00 p.m. PST)nField applications engineers: contact your local Altera sales officenReceive literature by mail: (888) 3-ALTERAnFTP: nWorld-wide web: -Use solutions to search for answers to technical problems -View design examples