Verilog第七章答案

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1、数字系统设计与Verilog HDL第七章答案（第6版）7.2module dflip(d,clk,q);input d,clk;output reg q;always (posedge clk)beginq=d;end endmodule /sturct design /*module dflip(d,clk,q,q_n);input d,clk;output q,q_n;/nand (out,input1,input2);/the struct of logic designwire g5,g6;nand G1 (q_n.g5,q) ;nand G2 (q,g6,q_n) ;nand G3

2、 (g5,clk,g6);nand G4 (g6,clk,d) ;endmodule */module D_Test(in,out,clk);input clk;input in;output 7:0out;dflip u1(.d(in),.clk(clk),.q(out1);dflip u2(.d(out1),.clk(clk),.q(out2);dflip u3(.d(out2),.clk(clk),.q(out3);dflip u4(.d(out3),.clk(clk),.q(out4);dflip u5(.d(out4),.clk(clk),.q(out5);dflip u6(.d(o

3、ut5),.clk(clk),.q(out6);dflip u7(.d(out6),.clk(clk),.q(out7);dflip u8(.d(out7),.clk(clk),.q(out0);endmodule7.3/*module JK_Model(clk,j,k,Q);input clk;input j,k;output Q;reg Q;always(posedge clk)Q=j&(Q)|(k)&Q;endmodule */module JK_Model(clk,j,k,Q,rs,set);input clk,j,k,set,rs;output Q;reg Q;always(pose

4、dge clk or negedge rs or negedge set)beginif(!rs)Q=1b0;else if(!set)Q=1b1;else case(j,k)2b00:Q=Q;2b01:Q=1b0;2b10:Q=1b1;2b11:Q=Q;default:Q=1bx;endcaseendendmodule7.4module Counter5(clk,reset,car,out);/car jup loadinput clk,reset;output car,out;reg2:0cnt;reg car;wire2:0out;assign out=cnt;always(posedg

5、e clk or negedge reset)beginif(!reset)begincnt=3b000;car=0;endelse begin if(cnt=3b100)/model=5begincar=3b001;/upcnt=3b000;endelse begin cnt=cnt+3b001;car=3b000;endendendendmodule7.5module Ser_to_Par(clk,rst,in,out); input clk,rst; input in; output3:0 out; /wire3:0 out; reg 3:0 shiftreg; always(posed

6、ge clk or negedge rst) if(!rst) shiftreg=0; else begin shiftreg=shiftreg3:1,in;/mix (shiftreg3,2,1),in end assign out=shiftreg;endmodule7.6module Par_to_Ser(clk,rst,in,out);input clk,rst;input3:0in;output out;reg out;reg1:0i;always(posedge clk)beginif(rst)begini=2d0;out=1d0;endelse if(i=3)begin out=

7、ini;i=i+1;endendendmodule7.8module data(data_in,data_out);input 7:0 data_in;output 7:0 data_out;reg7:0 data_out;always (data_in)beginif(data_in7)data_out=(data_in)+1)|8h80;elsedata_out=data_in;endendmodule7.9module Light(clk,ledout,reset);input reset,clk;output7:0 ledout;integer i;reg7:0ledout;reg2:

8、0count;reg4:0count2;reg clkflag;reg1:0in;always(posedge clk)beginif(!reset)count=0;else if(count=3)beginclkflag=0;count=count+1;endelse if(count =7)beginclkflag=1;count=0;endelsebeginclkflag=1;count=count+1;endendalways(posedge clk)beginif(!reset)count2=0;else if(count2=7)beginin=2b00;count2=count2+

9、1;endelse if(count2=15)beginin=2b01;count2=count2+1;endelse if(count2=23)beginin=2b10;count2=count2+1;endelse if(count2=23)beginin=2b10;count2=0;endendalways(clkflag or count or in or reset)beginif(!reset)ledout=8h00;elsebegincase(in)2b00:if(clkflag) ledout=8hff; else ledout=8h00;2b01:case(count)h0:ledout=8h80;h1:ledout=8h40;h2:ledout=8h20;h3:ledout=8h10;h4:ledout=8h08;h5:ledout=8h04;h6:ledout=8h02;h7:ledout=8h01;default:ledout=8h00;endcase2b10:if(clkflag)ledout=8haa; else ledout=8h00; default:ledout=8h00;endcaseendendendmodule