AT89C51单片机中英文文献翻译

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1、 . . . The General Situation of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of

2、these microcontrollers make them suitable for such high-speed event-based applications.However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools env

3、ironment for the validation of these microcontrollers both at the component and at the system level. IntelPlatformEngineering department developed anobject-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not onl

4、y to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT

5、89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output

6、 operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontroller

7、s in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension

8、, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time appli

9、cations, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financia

10、llyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacementsof components are extremely expensive, as the devices are typically sealed in modu

11、les with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validatio

12、n necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process

13、can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vecto

14、r two-level interrupt architecture,a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM

15、, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Figure 1-2-1Block Diagram1.3Pin DescriptionVCC: Supply voltage.GND: Ground.Port 0: Port

16、0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program an

17、d data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytesduring program verification. External pullups are required during programverification.Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pullups.The P

18、ort 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives t

19、he low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inpu

20、ts. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current

21、(IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to ext

22、ernal data memory that uses 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pul

23、lups.The Port 3 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the

24、functions of various special featuresof the AT89C51 as listed below:RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG:Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This

25、 pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external DataMemory.

26、If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN:Program S

27、tore Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPP: ExternalAccess Enable. EA must be strap

28、ped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFHNote, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. The spinal receives the 12-vo

29、lt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit.XTAL2: Output form the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the

30、 input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven

31、as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU

32、puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should b

33、e noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is

34、 not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode:In the power-down mode, the oscillator is stopped

35、, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change the on-chip RAM.

36、 The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the on-chip

37、Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmsBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following

38、steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or t

39、he lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 Ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle.

40、 During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initia

41、ted. 2.1Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not

42、been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Figure 2-1-1Programming the Flash Figure 2-2-2Verifying the Fl

43、ash2.2 Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Si

44、gnature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows:(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FF

45、H indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will autom

46、atically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be bro

47、ken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form

48、 which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interf

49、ace, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine wh

50、ich supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a

51、DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more approp

52、riate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to b

53、e connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to acc

54、ess information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPUs window to the outside.The most basic form of peripheral available on m

55、icrocontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Eachoutput pin

56、may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format

57、instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.AT89C51的概况1 AT89C51的应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备

58、集合使得它们适合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。强健的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的适宜的工具环境保证了高可靠性和低市场风险。Intel 平台工程部门开发了一种面向对象的用于验证它的 AT89C51 汽车单片机多线性测试环境。这种环境的目标不仅是为 AT89C51 汽车单片机提供一种强健的测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机的环境。开发的这种环境连接了 AT89C51。本文讨论了这种测试环境的设计和原理，它的和各种硬件/软件环境部件的交互性，以与如何使用 AT89C51。1.1 介绍8 位 A

59、T89C51 CHMOS 工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51 单片机典型地应用于高速事件控制系统。商业应用包括调制解调器、电动机控制系统、打印机、影印机、空调控制系统、磁盘驱动器和医疗设备。汽车工业把 MCS51 单片机用于发动机控制系统，悬挂系统和反锁制动系统。AT89C51尤其很好适用于得益于它的处理速度和增强型片的外围功能集，诸如：汽车动力控制、车辆动态悬挂、反锁制动和稳定性控制应用。由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的成本-效益控制器、服务大量时间和事件驱动的在实时应用中需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器

60、。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场，尤其在任务决定性应用诸如自动驾驶仪或反锁制动系统中，错误将是财力上所禁止的。重新设计的费用可以高达 500K 美元，如果产品族享有同样核和/或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题，在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。IntelChandler平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行

61、的测试类型。1.2 AT89C51提供以下标准功能：4 千字节的 FLASH (闪速存储器)、128字节的部 RAM （随机存取存储器）、32个I/O （输入/输出）接口线、2个16位定时/计数器、一个 5向量两级中断结构、一个全双工串行通信口、片振荡器与时钟电路。此外，AT89C51 降至 0Hz 的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制阻止 CPU 的工作，但允许 RAM（随机存取存储器）、定时/计数器、串行通信口与中断系统继续运行。掉电方式保存 RAM 中的容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。图1-2-1AT89C51 方框图1.3引脚功能说明

62、VCC：电源电压GND：地Port0：P0 是一组 8 位漏极开路型双向 I/O （输入/输出）口，也即地址/数据总线复用。作为输出口用时，每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8 位）和数据总线复用，在访问期间激活部上拉电阻。在Flash 编程时，P0 口承受指令字节，而在程序校验时，输出指令字节。校验时，要求外接上拉电阻。Port1：P1 是一个带部上拉电阻的8 位双向I/O（输入/输出）口，P1 的输出缓冲级可驱动（吸收或输出电流）4个TTL 逻辑门电路。对端口写“1”，通过部的上拉

63、电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。Flash 编程和程序校验期间，P1 承受低8 位地址。Port2：P2 是一个带有部上拉电阻的8 位双向I/O（输入/输出）口，P2 的输出缓冲级可驱动（吸收或输出电流）4个TTL 逻辑门电路。对端口写“1”，通过部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16 位四肢的外部数据存储器（例如执行MOVX DPTR指令）时，P2 口送出高8 位地址数据，在访问

64、8 位地址的外部数据存储器（例如执行MOVX RI 指令）时，P2 口线上的容（也即特殊功能寄存器（SFR）区中R2 寄存器的容），在整个访问期间不改变。Flash 编程和程序校验时，P2 也接收高位地址和其他控制信号。Port3：P3 是一个带有部上拉电阻的8 位双向I/O 口，P3 的输出缓冲级可驱动（吸收或输出电流）4个TTL 逻辑门电路。对端口写“1”，通过部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。P3 口还接收一些用于Flash （闪速存储器）编程和程序校验的控制信号。RST：复位输入。当振荡

65、器工作时，RST 引脚出现两个机器周期以上高电平将使单片机复位。ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低 8 位字节。即使不访问外部存储器，ALE 仍以时钟振荡频率的1/6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是，每当访问外部数据存储器时将跳过一个 ALE 脉冲。对 Flash 存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，通过对特殊功能寄存器（SFR）区中的8EH 单元 D0 位置设定，可禁止ALE 操作。该位置设定后，只有一条 MOVX 和 MOVC 指令 ALE 才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE 无效。PSEN：程序存储允许输出是外部程序存储器的读选通型号，当 AT89C51 由外部存储器取指令（或数据）时，每个机器周期 PSEN 被激活两次，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的PSEN 信号不出现。EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000HFFFFH），EA 端必须保持低电平（接地）。但需要注意的是：如果加密位LB1 被编程，复位时部会锁存 EA 端状态。如 EA 端为高电