北理工VHDL实验报告

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1、本科实验报告实验名称：VHDL语言与集成电路设计实验课程名称：VHDL语言与集成电路设计实验时间：2014.5任课教师：桂小琰实验地点：4-427实验教师：任仕伟实验类型： 原理验证 综合设计 自主创新学生_学号/_组 号：学院：信息与电子学院同组搭档：专 业：电子科学与技术成 绩：实验一：带有异步复位端的D触发器一、实验目的1熟悉linux操作环境和modelsim软件环境2理解时序逻辑和组合逻辑电路的区别3理解并行语句和顺序语句4用VHDL语言编写一个带有异步复位端的D触发器与其测试文件二、实验原理1组合逻辑和时序逻辑组合逻辑电路当前输出的值仅取决于当前的输入,不需要触发器等具有存储能力的

2、逻辑单元,仅仅使用组合逻辑门时序逻辑电路的当前输出不仅取决于当前的输入,还与以前的输入有关,这类电路中包括寄存器等元件,也包括组合逻辑电路,寄存器通过一个反馈环和组合逻辑模块相连.触发器便是属于时序逻辑电路2并行和顺序代码从本质上讲,VHDL代码是并发执行的.只有PROCESS,FUNCTION或PROCEDURE内的代码才是顺序执行的.当它们作为一个整体时,与其他模块之间又是并发执行的.以下是3个并发描述语句stat1,stat2和stat3的代码,会产生同样的电路结构.stat1stat3stat1stat2 = stat2 = stat3 = 其他排列顺序stat3stat1stat23

3、并行语句进程PROCESS语法结构：进程名: PROCESS 变量说明语句BEGINEND PROCESS 进程名；PROCESS 的特点1多进程之间是并行执行的；2进程结构内部的所有语句都是顺序执行的；3进程中可访问结构体或实体中所定义的信号；4进程的启动是由敏感信号列表所标明的信号来触发,也可以用WAIT语句等待一个触发条件的成立.5各进程之间的通信是由信号来传递的.4带有异步复位端的D触发器 电路符号功能表RDCPQ0xx01x0保持1x1保持10上升沿011上升沿1三、实验代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff ISP

4、ORT;END dff;ARCHITECTURE behavior OF dff IS BEGIN PROCESS BEGIN IF THEN q=0; ELSIF THEN q=d; END IF; END PROCESS; end ARCHITECTURE behavior;测试文件：library IEEE;use ieee.std_logic_1164.all;entity dff_tb is end dff_tb;architecture tb_behavior of dff_tb isponent dff port;end ponent;constant clk_period:ti

5、me:=50 ns;signal d,clk,q,rst:std_logic;begin dut:dff port mapd,clk=clk,rst=rst,q=q; clk_gen:process begin clk=0; wait for clk_period/2; clk=1; wait for clk_period/2; end process; d_gen:process begin wait for 100 ns; d=1; wait for 100 ns; d=0; end process; rst_gen:process begin rst=1; wait for 150 ns

6、; rst=0; wait for 500 ns; rst=1; wait for 150 ns; wait; end process;end tb_behavior;四、仿真结果实验二 步进电机控制器一、实验目的1理解两种状态机的区别2熟悉两种编程风格3编写BCD计数器和步进电机二、实验原理1米里型状态机和摩尔型状态机米里Mealy型状态机:状态机的输出信号不仅与电路的当前状态有关,还与当前的输入有关摩尔Moore型状态机：状态机的当前输出仅仅由当前状态决定2有限状态机设计流程：1 理解问题背景.2 逻辑抽象,得出状态转移图.3 状态简化.4 状态分配.5 用VHDL来描述有限状态机.3BC

7、D计数器原理图4步进电机控制器原理图步进电机状态与输出信号的对应关系状态输出状态S0S1S2S30001001001001000三、实验代码1BCD计数器library ieee;use ieee.std_logic_1164.all;entity counter is portclk,rst:in std_logic;count:out std_logic_vector;end counter;architecture state_machine of counter istype state is;signal pr_state,nx_state:state;begin process b

8、egin ifthen pr_state=nx_state; end if; end process; process begin case pr_state is when zero = count =0000; nx_state count =0001; nx_state count =0010; nx_state count =0011; nx_state count =0100; nx_state count =0101; nx_state count =0110; nx_state count =0111; nx_state count =1000; nx_state count =

9、1001; nx_state = zero; end case; end process; end state_machine;2步进电机控制器library ieee;use ieee.std_logic_1164.all;entity stepmotor is portclk,rst,x:in std_logic;output:out std_logic_vector;end stepmotor;architecture state_machine of stepmotor istype state is;signal pr_state,nx_state:state;begin proce

10、ss begin ifthen pr_state=s0; elsifthen pr_state=nx_state; end if; end process; process begin ifthen case pr_state is when s0 = output =0001; nx_state output =0010; nx_state output =0100; nx_state output =1000; nx_state = s2; end case; elsif then case pr_state is when s0 = output =0001; nx_state outp

11、ut =0010; nx_state output =0100; nx_state output =1000; nx_state = s0; end case; end if; end process; end state_machine;四、仿真结果BCD计数器步进电机控制器实验三 十六位加法器设计一、实验目的1掌握元件例化的方法2理解for/generate语句的用法3编程完成4位加法器和16位加法器的设计二、实验原理1元件的例化元件声明是对VHDL模块即底层设计,也是完整的VHDL设计的说明,使之可在其他被调用,元件声明可放在程序包中,也可在某个设计的构造体中声明.元件例化指元件的调用.

12、元件声明与元件例化的语法分别如下：元件声明：ponent元件实体名prot元件端口信息,同该元件实现时的实体的port部分；endpnent；元件例化：例化名：实体名,即元件名portmap端口列表；2生成语句GENERATEGENERATE语句用于循环执行某项操作.FOR模式的生成语句主要用于相同结构的描述中；FOR模式语法结构：FOR/GENERATE:标号：FOR 变量IN 离散区间GENERATE并行处理语句；END GENERATE；316位加法器的设计三、实验代码4位加法器：library ieee;use ieee.std_logic_1164.all;entity adder4

13、 is porta,b:in std_logic_vector; cin:in std_logic; s:out std_logic_vector; cout:out std_logic;end adder4;architecture behav of adder4 issignal c: std_logic_vector;signal p: std_logic_vector;signal g: std_logic_vector;begin G1:for i in 0 to 3 generate p=a xor b; g=a and b; s=p xor c;end generate;c=ci

14、n;c=cin and p or g;c=cin and p and P or g and p or g;c=cin and p and Pand P or g and p and P or g and P or g;c=cin and p and Pand P and P or g and p and P and P or g and P and P or g and P or g;cout=c;end behav;16位加法器：library ieee;use ieee.std_logic_1164.all;entity adder is porta,b:in std_logic_vect

15、or; s:out std_logic_vector; cin:in std_logic; cout:out std_logic;end adder;architecture behav of adder isponent adder4 is porta,b:in std_logic_vector; s:out std_logic_vector; cin:in std_logic; cout:out std_logic;end ponent;signal m1,m2,m3:std_logic;begin u1:adder4 port mapa,b,s,cin,m1; u2:adder4 por

16、t mapa,b,s,m1,m2; u3:adder4 port mapa,b,s,m2,m3; u4:adder4 port mapa,b,s,m3,cout;end behav;测试程序:library ieee;use ieee.std_logic_1164.all;entity adder_tb isend entity adder_tb;architecture behav of adder_tb isponent adder porta,b:in std_logic_vector; s:out std_logic_vector; cin:in std_logic; cout:out

17、 std_logic;end ponent;signal clk:std_logic:=0;signal a,b:std_logic_vector;signal s:std_logic_vector;signal cin:std_logic;signal cout: std_logic;begin w: adder port mapa,b=b,s=s,cin=cin,cout=cout ;processbegin a=x0000; b=x0000; cin=1; wait for 100ns; b= cin=0; wait for 100ns; a=x1111; b=x1111; cin=1;

18、 wait for 100ns; cin=1; wait ; end process;end behav;四、仿真结果实验四 选择运算器一、实验目的：1对前几次实验用到的知识进行总结2综合运用理论课上的知识,完成选择运算器的设计二、实验原理1设计要求：输出信号：一个COUT15:0 ,16位乘法器：要求用部分积实现加法器：8位加法器,高7位补零完成比较器、乘法器、加法器的设计,不可以直接使用+,x运算符直接实现.2选择器运算器总原理图如下：3乘法器部分采用并行乘法器4加法器：8位加法器的设计和上一个试验类似,先设计一个4位加法器,进而编译8位加法器.三、实验代码与门：library ieee;

19、use ieee.std_logic_1164.all;entity and_2 is port;end and_2;architecture behav of and_2 isbegin y= a and b;end behav; 全加器：library ieee;use ieee.std_logic_1164.all;entity fau is port;end fau;architecture behav of fau isbegin s=a xor b xor cin; cout=oror; end behav;顶层：library ieee;use ieee.std_logic_11

20、64.all;use work.my_ponents.all;entity top_row is porta:in std_logic; b:in std_logic_vector; sout,cout:out std_logic_vector; p:out std_logic; end top_row;architecture behav of top_row isbegin u1:ponent and_2 port mapa,b,sout; u2:ponent and_2 port mapa,b,sout; u3:ponent and_2 port mapa,b,sout; u4:pone

21、nt and_2 port mapa,b,sout; u5:ponent and_2 port mapa,b,sout; u6:ponent and_2 port mapa,b,sout; u7:ponent and_2 port mapa,b,sout; u8:ponent and_2 port mapa,b,p; u9:for i in 0 to 6 generate cout=0; end generate;end behav;中层：library ieee;use ieee.std_logic_1164.all;use work.my_ponents.all;entity mid_ro

22、w is porta:in std_logic; b:in std_logic_vector; sin,cin:in std_logic_vector; sout,cout:out std_logic_vector; p:out std_logic; end mid_row;architecture behav of mid_row issignal and_out:std_logic_vector;begin u1:ponent and_2 port mapa,b,sout; u2:ponent and_2 port mapa,b,and_out; u3:ponent and_2 port

23、mapa,b,and_out; u4:ponent and_2 port mapa,b,and_out; u5:ponent and_2 port mapa,b,and_out; u6:ponent and_2 port mapa,b,and_out; u7:ponent and_2 port mapa,b,and_out; u8:ponent and_2 port mapa,b,and_out; u9:ponent fau port mapsin,cin,and_out,sout,cout; u10:ponent fau port mapsin,cin,and_out,sout,cout;

24、u11:ponent fau port mapsin,cin,and_out,sout,cout; u12:ponent fau port mapsin,cin,and_out,sout,cout; u13:ponent fau port mapsin,cin,and_out,sout,cout; u14:ponent fau port mapsin,cin,and_out,sout,cout; u15:ponent fau port mapsin,cin,and_out,p,cout; end behav;底层：library ieee;use ieee.std_logic_1164.all

25、;use work.my_ponents.all;entity lower_row is portsin,cin:in std_logic_vector; p:out std_logic_vector;end lower_row;architecture behav of lower_row is signal local:std_logic_vector;beginlocal=0;u1:ponent fau port mapsin,cin,local,p,local; u2:ponent fau port mapsin,cin,local,p,local; u3:ponent fau por

26、t mapsin,cin,local,p,local; u4:ponent fau port mapsin,cin,local,p,local;u5:ponent fau port mapsin,cin,local,p,local; u6:ponent fau port mapsin,cin,local,p,local; u7:ponent fau port mapsin,cin,local,p,p; end behav;乘法器用到的的元件声明：library ieee;use ieee.std_logic_1164.all;package my_ponents isponent and_2

27、is port; end ponent; ponent fau is port; end ponent; ponent top_row is porta:in std_logic; b:in std_logic_vector; sout,cout:out std_logic_vector; p:out std_logic; end ponent; ponent mid_row is porta:in std_logic; b:in std_logic_vector; sin,cin:in std_logic_vector; sout,cout:out std_logic_vector; p:o

28、ut std_logic; end ponent; ponent lower_row is portsin,cin:in std_logic_vector; p:out std_logic_vector; end ponent; end my_ponents;乘法器：library ieee;use ieee.std_logic_1164.all;use work.my_ponents.all;entity multiplier is porta,b:in std_logic_vector; prod:out std_logic_vector;end multiplier;architectu

29、re behav of multiplier istype matrix is array of std_logic_vector;signal s,c:matrix;beginu1:ponent top_row port mapa,b,s,c,prod;u2:ponent mid_row port mapa,b,s,c,s,c,prod;u3:ponent mid_row port mapa,b,s,c,s,c,prod;u4:ponent mid_row port mapa,b,s,c,s,c,prod;u5:ponent mid_row port mapa,b,s,c,s,c,prod;

30、u6:ponent mid_row port mapa,b,s,c,s,c,prod;u7:ponent mid_row port mapa,b,s,c,s,c,prod;u8:ponent mid_row port mapa,b,s,c,s,c,prod;u9:ponent lower_row port maps,c,prod;end behav;4位加法器：library ieee;use ieee.std_logic_1164.all;entity adder4 is porta,b:in std_logic_vector; cin:in std_logic; s:out std_log

31、ic_vector; cout:out std_logic;end adder4;architecture behav of adder4 issignal c: std_logic_vector;signal p: std_logic_vector;signal g: std_logic_vector;begin G1:for i in 0 to 3 generate p=a xor b; g=a and b; s=p xor c;end generate;c=cin;c=cin and p or g;c=cin and p and P or g and p or g;c=cin and p

32、 and Pand P or g and p and P or g and P or g;c=cin and p and Pand P and P or g and p and P and P or g and P and P or g and P or g;cout=c;end behav;8位加法器：library ieee;use ieee.std_logic_1164.all;entity adder is porta,b:in std_logic_vector; s:out std_logic_vector; cin:in std_logic; cout:out std_logic;

33、end adder;architecture behav of adder isponent adder4 is porta,b:in std_logic_vector; s:out std_logic_vector; cin:in std_logic; cout:out std_logic;end ponent;signal m1,m2,m3:std_logic;begin u1:adder4 port mapa,b,s,cin,m1; u2:adder4 port mapa,b,s,m1,cout;end behav;选择运算器用到的元件声明：library ieee;use ieee.s

34、td_logic_1164.all;package my_ponents_1 is ponent multiplier is porta,b:in std_logic_vector ; prod:out std_logic_vector; end ponent; ponent adder is porta,b:in std_logic_vector; s:out std_logic_vector; cin:in std_logic; cout:out std_logic; end ponent;end my_ponents_1;选择运算器：library ieee;use ieee.std_l

35、ogic_1164.all;use work.my_ponents_1.all;entity operation is porta,b: in std_logic_vector; cout: out std_logic_vector;end operation;architecture behav of operation is signal w1:std_logic_vector; signal w2:std_logic_vector; signal w3:std_logic ; signal flag:integer range 1 to 3 :=3;begin u1:ponent mul

36、tiplier port map; u2:ponent adder port map; process begin ifbthen flag=1; elsifathen flag=2; else flag=3; end if; end process; with flag select cout= w1 when 1, 0000000& w3 & w2 when 2, 0when others;end behav;测试文件：library ieee;use ieee.std_logic_1164.all;entity operation_tb isend operation_tb;archit

37、ecture behav of operation_tb is ponent operation porta,b:in std_logic_vector; cout:out std_logic_vector;end ponent;signal a,b:std_logic_vector;signal cout:std_logic_vector;begin w:operation port mapa,b=b,cout=cout; input_gen:process begin a=01111111; b=00000001; wait for 100 ns; a=00001111; b=010000

38、01; wait for 100 ns; a=10101010; b=10101010; wait for 100 ns; a=11100100; b=10101010; wait for 100 ns; a=00101010; b=10101010; wait for 100 ns; a=11101111; b=11101111; wait for 100 ns; wait; end process;end ;四、仿真结果五、总结与感悟 通过这4周的实验,我对VHDL语言有了更加深刻的理解,同时对linux操作系统有了一定了解.在实践中,我对理论知识理解薄弱的地方进行了加强,例如元件的声明和例化ponent语句不属于书面的考试范围,我一直对其理解的不充分,但是通过后两次的实验,我逐渐掌握了这部分知识,这充分说明了学习VHDL语言时,必须经常自己动手编程,在实践中不断查漏补缺. 很感谢桂老师和任老师的悉心教导,让我对这门语言产生了充分的兴趣,学到了很多有用的知识.17 / 17