操作系统精髓与设计原理第五版课后答案英文版.pdf

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1、SOLUTIONS MANUAL OPERATING SYSTEMS: INTERNALS AND DESIGN PRINCIPLES FIFTH EDITION WILLIAM STALLINGS Copyright 2004: William Stallings -2- 2004 by William Stallings All rights reserved. No part of this document may be reproduced, in any form or by any means, or posted on the Internet, without permiss

2、ion in writing from the author. -3- NOTICE This manual contains solutions to all of the review questions and homework problems in Operating Systems, Fifth Edition. If you spot an error in a solution or in the wording of a problem, I would greatly appreciate it if you would forward the information vi

3、a email to me at . An errata sheet for this manual, if needed, is available at ftp:/ W.S. -4- TABLE OF CONTENTS Chapter 1: Computer System Overview.5 Chapter 2: Operating System Overview .11 Chapter 3: Process Description and Control .14 Chapter 4: Threads, SMP, and Microkernels.18 Chapter 5: Concur

4、rency: Mutual Exclusion and Synchronization.21 Chapter 6: Concurrency: Deadlock and Starvation.30 Chapter 7: Memory Management.38 Chapter 8: Virtual Memory.43 Chapter 9: Uniprocessor Scheduling .51 Chapter 10: Multiprocessor and Real-Time Scheduling.62 Chapter 11: I/O Management and Disk Scheduling.

5、65 Chapter 12: File Management.71 Chapter 13: Networking.74 Chapter 14: Distributed Processing, Client/Server, and Clusters.76 Chapter 15: Distributed Process Management.79 Chapter 16: Security .82 -5- ANSWERS TO QUESTIONS 1.1 A main memory, which stores both data and instructions: an arithmetic and

6、 logic unit (ALU) capable of operating on binary data; a control unit, which interprets the instructions in memory and causes them to be executed; and input and output (I/O) equipment operated by the control unit. 1.2 User-visible registers: Enable the machine- or assembly-language programmer to min

7、imize main memory references by optimizing register use. For high-level languages, an optimizing compiler will attempt to make intelligent choices of which variables to assign to registers and which to main memory locations. Some high- level languages, such as C, allow the programmer to suggest to t

8、he compiler which variables should be held in registers. Control and status registers: Used by the processor to control the operation of the processor and by privileged, operating system routines to control the execution of programs. 1.3 These actions fall into four categories: Processor-memory: Dat

9、a may be transferred from processor to memory or from memory to processor. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. Data processing: The processor may perform some arithmetic or logic operation on data. Control: An

10、 instruction may specify that the sequence of execution be altered. 1.4 An interrupt is a mechanism by which other modules (I/O, memory) may interrupt the normal sequencing of the processor. 1.5 Two approaches can be taken to dealing with multiple interrupts. The first is to disable interrupts while

11、 an interrupt is being processed. A second approach is to define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be interrupted. 1.6 The three key characteristics of memory are cost, capacity, and access time. 1.7 Cache memory is

12、a memory that is smaller and faster than main memory and that is interposed between the processor and main memory. The cache acts as a buffer for recently used memory locations. 1.8 Programmed I/O: The processor issues an I/O command, on behalf of a process, to an I/O module; that process then busy-

13、waits for the operation to be completed before proceeding. Interrupt-driven I/O: The processor issues an I/O command on behalf of a process, continues to execute subsequent instructions, and is interrupted by the I/O module when the latter has completed its work. The subsequent instructions may be i

14、n the same process, if it is not necessary for that process to wait for the completion of the I/O. Otherwise, the process is suspended pending the interrupt and other work is performed. Direct memory access (DMA): A DMA CHAPTER 1 COMPUTER SYSTEM OVERVIEW -6- module controls the exchange of data betw

15、een main memory and an I/O module. The processor sends a request for the transfer of a block of data to the DMA module and is interrupted only after the entire block has been transferred. 1.9 Spatial locality refers to the tendency of execution to involve a number of memory locations that are cluste

16、red. Temporal locality refers to the tendency for a processor to access memory locations that have been used recently. 1.10 Spatial locality is generally exploited by using larger cache blocks and by incorporating prefetching mechanisms (fetching items of anticipated use) into the cache control logi

17、c. Temporal locality is exploited by keeping recently used instruction and data values in cache memory and by exploiting a cache hierarchy. ANSWERS TO PROBLEMS 1.1 Memory (contents in hex): 300: 3005; 301: 5940; 302: 7006 Step 1: 3005 IR; Step 2: 3 AC Step 3: 5940 IR; Step 4: 3 + 2 = 5 AC Step 5: 70

18、06 IR; Step 6: AC Device 6 1.2 1. a. The PC contains 300, the address of the first instruction. This value is loaded in to the MAR. b. The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be don

19、e in parallel. c. The value in the MBR is loaded into the IR. 2. a. The address portion of the IR (940) is loaded into the MAR. b. The value in location 940 is loaded into the MBR. c. The value in the MBR is loaded into the AC. 3. a. The value in the PC (301) is loaded in to the MAR. b. The value in

20、 location 301 (which is the instruction with the value 5941) is loaded into the MBR, and the PC is incremented. c. The value in the MBR is loaded into the IR. 4. a. The address portion of the IR (941) is loaded into the MAR. b. The value in location 941 is loaded into the MBR. c. The old value of th

21、e AC and the value of location MBR are added and the result is stored in the AC. 5. a. The value in the PC (302) is loaded in to the MAR. b. The value in location 302 (which is the instruction with the value 2941) is loaded into the MBR, and the PC is incremented. c. The value in the MBR is loaded i

22、nto the IR. 6. a. The address portion of the IR (941) is loaded into the MAR. b. The value in the AC is loaded into the MBR. c. The value in the MBR is stored in location 941. 1.3 a. 2 24 = 16 MBytes b. (1) If the local address bus is 32 bits, the whole address can be transferred at once and decoded

23、 in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand. -7- (2) The 16 bits of the address placed on the address bus cant access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the

24、 address and then the second part (since the microprocessor will end in two steps). For a 32-bit address, one may assume the first half will decode to access a row in memory, while the second half is sent later to access a column in memory. In addition to the two-step address operation, the micropro

25、cessor will need 2 cycles to fetch the 32 bit instruction/operand. c. The program counter must be at least 24 bits. Typically, a 32-bit microprocessor will have a 32-bit external address bus and a 32-bit program counter, unless on- chip segment registers are used that may work with a smaller program

26、 counter. If the instruction register is to contain the whole instruction, it will have to be 32-bits long; if it will contain only the op code (called the op code register) then it will have to be 8 bits long. 1.4 In cases (a) and (b), the microprocessor will be able to access 2 16 = 64K bytes; the

27、 only difference is that with an 8-bit memory each access will transfer a byte, while with a 16-bit memory an access may transfer a byte or a 16-byte word. For case (c), separate input and output instructions are needed, whose execution will generate separate I/O signals (different from the memory s

28、ignals generated with the execution of memory-type instructions); at a minimum, one additional output pin will be required to carry this new signal. For case (d), it can support 2 8 = 256 input and 2 8 = 256 output byte ports and the same number of input and output 16-bit ports; in either case, the

29、distinction between an input and an output port is defined by the different signal that the executed input or output instruction generated. 1.5 Clock cycle = 1 8 MHz = 125 ns Bus cycle = 4 125 ns = 500 ns 2 bytes transferred every 500 ns; thus transfer rate = 4 MBytes/sec Doubling the frequency may

30、mean adopting a new chip manufacturing technology (assuming each instructions will have the same number of clock cycles); doubling the external data bus means wider (maybe newer) on-chip data bus drivers/latches and modifications to the bus control logic. In the first case, the speed of the memory c

31、hips will also need to double (roughly) not to slow down the microprocessor; in the second case, the wordlength of the memory will have to double to be able to send/receive 32-bit quantities. 1.6 a. Input from the Teletype is stored in INPR. The INPR will only accept data from the Teletype when FGI=

32、0. When data arrives, it is stored in INPR, and FGI is set to 1. The CPU periodically checks FGI. If FGI =1, the CPU transfers the contents of INPR to the AC and sets FGI to 0. When the CPU has data to send to the Teletype, it checks FGO. If FGO = 0, the CPU must wait. If FGO = 1, the CPU transfers

33、the contents of the AC to OUTR and sets FGO to 0. The Teletype sets FGI to 1 after the word is printed. b. The process described in (a) is very wasteful. The CPU, which is much faster than the Teletype, must repeatedly check FGI and FGO. If interrupts are used, the Teletype can issue an interrupt to

34、 the CPU whenever it is ready to accept or send data. The IEN register can be set by the CPU (under programmer control) -8- 1.7 If a processor is held up in attempting to read or write memory, usually no damage occurs except a slight loss of time. However, a DMA transfer may be to or from a device t

35、hat is receiving or sending data in a stream (e.g., disk or tape), and cannot be stopped. Thus, if the DMA module is held up (denied continuing access to main memory), data will be lost. 1.8 Let us ignore data read/write operations and assume the processor only fetches instructions. Then the process

36、or needs access to main memory once every microsecond. The DMA module is transferring characters at a rate of 1200 characters per second, or one every 833 s. The DMA therefore steals every 833rd cycle. This slows down the processor approximately 1 833 100% = 0.12% 1.9 a. The processor can only devot

37、e 5% of its time to I/O. Thus the maximum I/O instruction execution rate is 10 6 0.05 = 50,000 instructions per second. The I/O transfer rate is therefore 25,000 words/second. b. The number of machine cycles available for DMA control is 10 6 (0.05 5 + 0.95 2) = 2.15 10 6 If we assume that the DMA mo

38、dule can use all of these cycles, and ignore any setup or status-checking time, then this value is the maximum I/O transfer rate. 1.10 a. A reference to the first instruction is immediately followed by a reference to the second. b. The ten accesses to ai within the inner for loop which occur within

39、a short interval of time. 1.11 Define C i = Average cost per bit, memory level i S i = Size of memory level i T i = Time to access a word in memory level i H i = Probability that a word is in memory i and in no higher-level memory B i = Time to transfer a block of data from memory level (i + 1) to m

40、emory level i Let cache be memory level 1; main memory, memory level 2; and so on, for a total of N levels of memory. Then C s = C i S i i=1 N S i i=1 N The derivation of T s is more complicated. We begin with the result from probability theory that: Expected Value of x = i Pr x = 1 i=1 N -9- We can

41、 write: T s = T i H i i=1 N We need to realize that if a word is in M 1 (cache), it is read immediately. If it is in M 2 but not M 1 , then a block of data is transferred from M 2 to M 1 and then read. Thus: T 2 = B 1 + T 1 Further T 3 = B 2 + T 2 = B 1 + B 2 + T 1 Generalizing: T i = B j + T 1 j=1

42、i1 So T s = B j H i ( ) j=1 i1 i=2 N + T 1 H i i=1 N But H i i=1 N = 1 Finally T s = B j H i ( ) j=1 i1 i=2 N + T 1 1.12 a. Cost = C m 8 10 6 = 8 10 3 = $80 b. Cost = C c 8 10 6 = 8 10 4 = $800 c. From Equation 1.1 : 1.1 T 1 = T 1 + (1 H)T 2 (0.1)(100) = (1 H)(1200) H = 1190/1200 1.13 There are thre

43、e cases to consider: Location of referenced word Probability Total time for access in ns In cache 0.9 20 Not in cache, but in main memory (0.1)(0.6) = 0.06 60 + 20 = 80 Not in cache or main memory (0.1)(0.4) = 0.04 12ms + 60 + 20 = 12,000,080 So the average access time would be: Avg = (0.9)(20) + (0

44、.06)(80) + (0.04)(12000080) = 480026 ns -10- 1.14 Yes, if the stack is only used to hold the return address. If the stack is also used to pass parameters, then the scheme will work only if it is the control unit that removes parameters, rather than machine instructions. In the latter case, the proce

45、ssor would need both a parameter and the PC on top of the stack at the same time. -11- ANSWERS TO QUESTIONS 2.1 Convenience: An operating system makes a computer more convenient to use. Efficiency: An operating system allows the computer system resources to be used in an efficient manner. Ability to

46、 evolve: An operating system should be constructed in such a way as to permit the effective development, testing, and introduction of new system functions without interfering with service. 2.2 The kernel is a portion of the operating system that includes the most heavily used portions of software. G

47、enerally, the kernel is maintained permanently in main memory. The kernel runs in a privileged mode and responds to calls from processes and interrupts from devices. 2.3 Multiprogramming is a mode of operation that provides for the interleaved execution of two or more computer programs by a single p

48、rocessor. 2.4 A process is a program in execution. A process is controlled and scheduled by the operating system. 2.5 The execution context, or process state, is the internal data by which the operating system is able to supervise and control the process. This internal information is separated from

49、the process, because the operating system has information not permitted to the process. The context includes all of the information that the operating system needs to manage the process and that the processor needs to execute the process properly. The context includes the contents of the various pro

50、cessor registers, such as the program counter and data registers. It also includes information of use to the operating system, such as the priority of the process and whether the process is waiting for the completion of a particular I/O event. 2.6 Process isolation: The operating system must prevent

51、 independent processes from interfering with each others memory, both data and instructions. Automatic allocation and management: Programs should be dynamically allocated across the memory hierarchy as required. Allocation should be transparent to the programmer. Thus, the programmer is relieved of

52、concerns relating to memory limitations, and the operating system can achieve efficiency by assigning memory to jobs only as needed. Support of modular programming: Programmers should be able to define program modules, and to create, destroy, and alter the size of modules dynamically. Protection and

53、 access control: Sharing of memory, at any level of the memory hierarchy, creates the potential for one program to address the memory space of another. This is desirable when sharing is needed by particular applications. At other times, it threatens the integrity of programs and even of the operatin

54、g system itself. The operating system must allow portions of memory to be accessible in various ways by various users. Long-term storage: Many application programs require means for storing information for extended periods of time, after the computer has been powered down. CHAPTER 2 OPERATING SYSTEM

55、 OVERVIEW -12- 2.7 A virtual address refers to a memory location in virtual memory. That location is on disk and at some times in main memory. A real address is an address in main memory. 2.8 Round robin is a scheduling algorithm in which processes are activated in a fixed cyclic order; that is, all

56、 processes are in a circular queue. A process that cannot proceed because it is waiting for some event (e.g. termination of a child process or an input/output operation) returns control to the scheduler. 2.9 A monolithic kernel is a large kernel containing virtually the complete operating system, in

57、cluding scheduling, file system, device drivers, and memory management. All the functional components of the kernel have access to all of its internal data structures and routines. Typically, a monolithic kernel is implemented as a single process, with all elements sharing the same address space. A

58、microkernel is a small privileged operating system core that provides process scheduling, memory management, and communication services and relies on other processes to perform some of the functions traditionally associated with the operating system kernel. 2.10 Multithreading is a technique in whic

59、h a process, executing an application, is divided into threads that can run concurrently. ANSWERS TO PROBLEMS 2.1 The answers are the same for (a) and (b). Assume that although processor operations cannot overlap, I/O operations can. 1 Job: TAT = NT Processor utilization = 50% 2 Jobs: TAT = NT Proce

60、ssor utilization = 100% 4 Jobs: TAT = (2N 1)NT Processor utilization = 100% 2.2 I/O-bound programs use relatively little processor time and are therefore favored by the algorithm. However, if a processor-bound process is denied processor time for a sufficiently long period of time, the same algorith

61、m will grant the processor to that process since it has not used the processor at all in the recent past. Therefore, a processor-bound process will not be permanently denied access. 2.3 With time sharing, the concern is turnaround time. Time-slicing is preferred because it gives all processes access

62、 to the processor over a short period of time. In a batch system, the concern is with throughput, and the less context switching, the more processing time is available for the processes. Therefore, policies that minimize context switching are favored. 2.4 A system call is used by an application prog

63、ram to invoke a function provided by the operating system. Typically, the system call results in transfer to a system program that runs in kernel mode. 2.5 The system operator can review this quantity to determine the degree of stress on the system. By reducing the number of active jobs allowed on the system,